Clock to output delay tco for DFF

[Altera_Forum]

Hi all, 

 I have implemented a simple synchronous sequential logic, couple of gates and two FF. Quartus II by default uses Classic Timing Analyzer which shows a delay of ~4ns from clock input to data output for the D flip flop that is used to store state information. I don't know if this is min or max delay, and even if it is the guaranteed tco for the D flip flop. The tco I want is NOT device pin input to pin output, but the input to output of a DFF inside the CPLD. I/O Output Timing for Altera Devices-an366.pdf does not give this specific info. And I don't know how to setup Timing Analyzer (atleast not yet, trying to learn.) As an aside, this information is specified for discrete 14-pin DFF devices.  My experience level is beginner, I don't know any HDL, but I understand digital logic and use BDF to implement all logic. Target hardware is Max II EPM240, system clock is 10ns. Flip flop clock is 80ns.

[Altera_Forum]

--- Quote Start ---  Hi all,  I have implemented a simple synchronous sequential logic, couple of gates and two FF. Quartus II by default uses Classic Timing Analyzer which shows a delay of ~4ns from clock input to data output for the D flip flop that is used to store state information. I don't know if this is min or max delay, and even if it is the guaranteed tco for the D flip flop. The tco I want is NOT device pin input to pin output, but the input to output of a DFF inside the CPLD. I/O Output Timing for Altera Devices-an366.pdf does not give this specific info. And I don't know how to setup Timing Analyzer (atleast not yet, trying to learn.) As an aside, this information is specified for discrete 14-pin DFF devices.  My experience level is beginner, I don't know any HDL, but I understand digital logic and use BDF to implement all logic. Target hardware is Max II EPM240, system clock is 10ns. Flip flop clock is 80ns.  --- Quote End ---    Hi quintus,  why to want to know the tco of the registers inside the FPGA ? Quartus handles the internal timing for as long as you have set your design constraints.   BTW: How do you generate the Flip Flop clock ?  Kind regards  GPK

[Altera_Forum]

Hi, 

 Thanks for the reply. Sorry for my late reply, I forgot to check this thread for some time. I did not explain my original problem correctly. I had previously implemented a sequential logic network using discrete FF and AND gates. I was trying to port the same design on a CPLD.   The particular senario I am worried about is: I have two input signals which are generated by an external circuit. These signals are checked against a specific state transition inside the CPLD. The problem occurs when both input signals are transitioning from 0 to 1 (or 1 to 0) at the same time as the CPLD clock rising edge. One of the FF then will go into a metastable state and my output does not follow the state logic. But I found that if there is a FIXED delay between the input and output of the FF, the final logic output will not be affected, even if DFF goes metastable. Hence my question about tco of DFF.  The FF clock is multiple of system clock, generated by a counter.  I solved my original problem by putting sychronizing FF at the beginning of my logic to make sure the input signals are now adjusted to CPLD clock instead of the external clock, so clock transitions and input signal transitions don't occur at the same time (hopefully).