Hallo Everyone
This is my first FPGA project, so please forgive me if the question is silly, but i could not find any answer for last two days thats why i am posting here
I am desinging my block in simulink and then using the MATLAB HDL coder to generate the VHDL code. Then i tried the MATLAB HDL coder and the Quatras 2 software to synthesize my code. But the problem i am having is with my Fmax (The maximum frequency at which the circuit can be clocked). I get a Fmax of only 37.5 MHz. I tried all the optimization options and even tried simpler filter blocks, but Fmax is always below 50 MHz. Is there an way in between where i need specify the clock or something like that??? I am attaching the generated HDL code please let me know how to solve this issue and if you need some more information please feel free to ask me.
Both my input and output sampling frequency is 11.2 MHz in this case, for the other modules i want to make a set of interpolation filters with where the input will be 44.1 kHz and output of 11.2 MHz again
