Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Clocking with Cyclone 10 Hard IP for PCIe, NIOS II processors, and mSGDMA.


I have a project with several IP blocks in platform designer: Cyclone 10 Hard IP for PCIe, NIOS II, mSGDMA, emif, onchip memory, IOPLL, and LVDS. In Intel's example design for Hard IP for PCIe express, all clock inputs run off the "coreclkout_hip" of the PCIe hard IP. In this design if use the  "coreclkout_hip" to run NIOS II process and mSGDMA it will not pass timing requirements. I've tried passing the clock through a buffer but get the same results.


What are clocking strategies for using multiple IP blocks with Hard IP for PCIe?





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