Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Code Explanation Request.

Altera_Forum
Honored Contributor II
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It is probably very simple, but what does "f_gp_timer(f_gp_timer'high - 4)" in f_led_n <= (others => f_gp_timer(f_gp_timer'high - 4)) ; actually do, please? Could someone explain this to me please? Thank you.

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Altera_Forum
Honored Contributor II
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f_gp_timer'high means the highest bit number in a vector, eg., for signal "f_gp_timer : std_logic_vector(31 downto 0);" f_gp_timer'high is 31, so f_gp_timer(f_gp_timer'high - 4) just means the 4th bit from the MSB or in the case of the 32-bit vector example I just gave, bit 31-4=27. So the code is setting all bits in f_led_n to the state of the f_gp_timer MSB-4 bit. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Thank you very much, Dave!!!!

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