Congratulations you are already done. Easiest project you will ever have. Verilog is a proper subset of SystemVerilog, by design, so your verilog code should work as is.
I'm no expert, but there is a deeper answer if you really want , but why risk it if it already works and the benefits feels minuscule, especially with altera and if the point being to be able to compile the design for a newer ic or something..
So i'm using the Quartus software to program a DE1 SoC Cyclone 5 board, and I tried to just transfer it to SystemVerilog, and had errors after errors of it not understanding the language. Is there something that I'm doing wrong? Is it more than just copy & paste from my Verilog window to my SystemVerilog window?
A lot of them were syntax errors, just going though them slowly. couple of other issues it the always @ compared to always_ff @. I didn't save it as .sv, with Quartos it has a selection at the beginning to choose Verilog or SystemVerilog. I chose SystemVerilog, and just did a copy paste directly in. Which I would assume would be the same as saving with a .sv extension.