Combinational loop

[Altera_Forum]

When I start up Timing Analyzer GUI (quartus_staw) and read my sdc file I then try one of the reports (report clocks). I get a message saying "Critical Warning: Design contains combinational loop of 3414 nodes. Estimating the delay through the loop."  

 It then proceeds to estimate the delay ... F-O-R-E-V-E-R...rendering the the Timing Analyzer useless (Hey Altera, nice feature. You might want to add an option to disable the combinational loops at this point so that we can actually use the tool).  Anyway, I would like to disable this loop using either set_disable_timing or set_false_path. Problem is that the tool gives a node name not a port name.  For example: i_MPBLOCK_CUSTOM|u_mse2|u_alu|Add2~615|sumout  How do I convert this info to a port name that I can use with set_disable_timing or set_false_path.  I know that this path is invalid.

[Altera_Forum]

Can you please tell us if you explicitly introduced a combinatorial loop in your design? 

 If not. I suggest to modify the HDL code in order to remove the combinatorial loop.

[Altera_Forum]

If it were that simple I would have done so. It is in an IP block that we do not own and can not modify.

[Altera_Forum]

Some combinational loops in a design are quite normal, e.g. if you need asynchronous latches in a place. They regularly don't cause problem except a warning. There must be something special with your desígn to make the timing analysis fail.

[Altera_Forum]

Either way, how do I convert a node name to a port name so that I can either set_disable_timing or set_false_path? 

 This is just a simple tool question. How do I break a combinational loop so that I can make progress? Leave the long term solution up to me. For now, all I want to know is how to take the information the tool is spitting out (node name) and convert it to something I can use (port name) to break the combinational loop.  Once I have that I can actually use the tool to analyze what the real problem is. Right now the tool is dead in the water trying to estimate timing F-O-R-E-V-E-R.

[Altera_Forum]

Port names are top-level I/O, so I assume you don't want that. Probably a pin name? Use the Name Finder and it will give you names that exist. You might want to do a false path -through the name, as -from/to must be endpoints, while I assume you're looking at a combinatorial node. 

You're using IP that has never been analyzed in TimeQuest?  My guess is the reason there is no option to disable it is because it's normally not a problem. As FvM said, comb loops are in many designs and they go through. The tools probably already have too many options, so adding more for things that normally aren't a problem wouldn't make sense. (I think of the time there was a problem with Quartus synthesis running in the weeds and never finishing. After looking at the code, which was written by the user's internal high-level synthesis tool, there was a state-machine with 100,000 states. This was just not planned for by synthesis...)

[Altera_Forum]

Using Name Finder, I tried: 

set_false_path -through [get_nets {*cmd_done*}] and  set_false_path -from [get_registers {*instr_reg*}] -through [get_nets {*cmd_done*}] -to [get_registers {*exec_fsm*}] but both failed to stop the combinational loops. Name Finder is finding a set of targets and the command seems to be accepted without error when run. It just does not stop the combinational loops.  No the IP has not been analyzed in TimeQuest. It has been analyzed with synopsys and xilinx tools. Both do not stop running when they find combinational loops. They just give a warning and continue, like a good tool should ;^)  Is there really no way to turn off "estimating delay through combinational loop" in TimeQuest?  I am starting to believe that there is not. 

[Altera_Forum]

What version of the tool are you running? 

I don't know of any option, but again don't think it's normally an issue. I've seen some very ugly ASIC code go through without problem. Maybe file a Service Request to see if there's a back-door.

[Altera_Forum]

Currently I am using 7.2 on linux. I have downloaded 10.1 on my pc but have not tried it yet. Still trying to get Altera to cough up a license for 10.1 upgrade for us on linux. 

 If I can not disable combinational loops is there a good way to see what the combinational loop is? The output from Timequest only shows nodes which is a bit useless. I would love to see some net name list of the loop or a pictorial view of it. I just do not see it when I look at the code. Like I mentioned before, I do not own the code so getting it changed is the long term solution. Right now I would love to find a way to bypass the problem while I work the long term solution in parallel.

[Altera_Forum]

Conclusion to this issue was to go to the owners of the IP and get them to change their code to remove combinational loops. Nothing else worked. "set_disable_timing" and "set_false_path" did not work and as far as I can tell their are not switches in the tool that allow you to bypass the combinational loops.

[Altera_Forum]

Bujosa, 

 You did the right thing by asking the owner to modify the IP. This warning is serious and demonstrates bad design practices. Latches are ok and won't generate combinational nodes with more than two or three nodes. For TimeQuest to go into exponential time computation, you are dealing with a lot more nodes all connected into what is known as a strongly connected component in computer science. Basically when any node in the loop can get to any other node in the loop through a combinational path. TimeQuest is suppose to be smart enough to detect when the node is too large to try to analyze. This is important as a large enough strongly connected component can take as much time as stars in the universe :-)  Seems like the TimeQuest algorithm is estimating what it will tak incorrectly, and therefore trying to analyze it, instead of switching to the alternative algorithm where it does not try to analyze it exhaustively.   Anyway, I do believe there is a hidden QSF variable to change the threshold, but I don't have access to Quartus now and I don't remember it. But you can definetely use set_disable_timing to fix this problem. But because of the characteristics of the loop, you may need to cut several nodes ( or all of them ). TimeQuest should have givien you a message with the nodes in the loop. You should be able to copy and paste this names into a [get_nodes] collection. Set_false_path will only work to fix a report timing path ( a path between two registers) but won't prevent TimeQuest from analyzing it from some of the global reports that need to analyze the whole net list.  As I don't have access to Quartus to confirm my statements, I hope they are right, but if you post the full name of one of the nodes in the loop, we can help you with the right collection. Also note that you can use the Name Finder in TimeQuest to confirm the collections are correct.  Hope this helps.