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Altera_Forum
Honored Contributor I
1,019 Views

Compile Error in AOCL 17.0.2 environment

In the Intel FPGA SDK for OpenCL 16.1.2 version, our project can be compiled successfully. But when we update the software version into Intel FPGA SDK for OpenCL 17.0, the compiling is error! 

the information shown in the file 'quartus_sh_compile.log' is as follows: 

 

Error (18999): Placement cannot find a legal solution. Error (18999): Placement cannot find a legal solution. Error (18999): Placement cannot find a legal solution. Error (18999): Placement cannot find a legal solution. Info (170191): Fitter placement operations beginning Error (170077): Cannot place the following nodes Error (170078): Cannot place node "freeze_wrapper_inst|kernel_system_inst|webp_system|webp_system|microblock_encode_y_inst_0|kernel|themicroblock_encode_y_function|thebb_Block14_aunroll_x|thebb_Block14_stall_region|thei_sfc_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_enter46592_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit47096_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit4709611028_data_fifo_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit4709611029|fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b" of type EC with location constraints LogicLock Plus region freeze_wrapper_inst|kernel_system_inst from User-Defined LogicLock Plus Region File: /home/fanbaoyu/work/bak/webp-bak20170725-v3.0.2-max_8192/webp/bin/17.0/webp/tmp-clearbox/top_synth/2008/altsyncram_3fl1.tdf Line: 36 Error (170078): Cannot place node "freeze_wrapper_inst|kernel_system_inst|webp_system|webp_system|microblock_encode_y_inst_0|kernel|themicroblock_encode_y_function|thebb_Block14_aunroll_x|thebb_Block14_stall_region|thei_sfc_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_enter46592_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit47096_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit4709611028_data_fifo_aunroll_x|thei_acl_sfc_exit_c0_for_cond2_i763_preheader_unifiedlatchblock_switch_microblock_encode_y_c0_exit4709611029|fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b" of type EC with location constraints LogicLock Plus region freeze_wrapper_inst|kernel_system_inst from User-Defined LogicLock Plus Region File: /home/fanbaoyu/work/bak/webp-bak20170725-v3.0.2-max_8192/webp/bin/17.0/webp/tmp-clearbox/top_synth/2008/altsyncram_3fl1.tdf Line: 36 ... ... .... ... ... Info (170192): Fitter placement operations ending: elapsed time is 00:14:53 Info (11888): Total time spent on timing analysis during Placement is 2661.82 seconds. Error: An error occurred during placement Error: Quartus Prime Fitter was unsuccessful. 4869 errors, 328 warnings Error: Peak virtual memory: 41996 megabytes Error: Processing ended: Wed Aug 16 01:18:39 2017 Error: Elapsed time: 06:03:45 Error: Total CPU time (on all processors): 20:04:33 Info: *******************************************************************  

We don't know how to modified the **.cl file to repair this error? Could you give us some suggestion?  

 

Thanks!
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3 Replies
Altera_Forum
Honored Contributor I
83 Views

I had issues compiling when I bumped to 17.0 as well. I didn't see the error(s) that you are seeing but I did overlook the fact that the BSP I was using needed a specific update of Quartus 17.0. I needed 17.0.1 and was using 17.0.2. Have you verified the correct Quartus version with your BSP documentation? It's a long shot but worth checking.

Altera_Forum
Honored Contributor I
83 Views

The Support Request on mysupport.altera.com area lists !!! 10 !!! 17.x versions of the QuartusPrime when you open an SR. I also had a bug in 17.0 which is still not fixed. I would send this to your local FAE.

Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

I had issues compiling when I bumped to 17.0 as well. I didn't see the error(s) that you are seeing but I did overlook the fact that the BSP I was using needed a specific update of Quartus 17.0. I needed 17.0.1 and was using 17.0.2. Have you verified the correct Quartus version with your BSP documentation? It's a long shot but worth checking. 

--- Quote End ---  

 

 

This is certainly correct. For Arria 10, BSP version and Quartus version MUST match. Terasic, for instance, does not have a BSP for v17.0 or any of its subversions yet and hence, people using the Terasic DE5A-Net board should continue using Quartus v16.1.2.
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