Compiling openCl to RTL and then use as a function (instead of C2H)

[Altera_Forum]

I have a standalone classic VHDL / Nios project with DDR2 and ethernet that has been in production for a while. 

Now, we need to add compression to the stream. I was thinking about adding a openCl core to the design, but it seems that the openCl compiler may not replace the old C2H? (have not digged into the openCl for Altera yet, but do have quite a few openCl kernels out there).  Am I right to assume that: 1, I need an external host to run the OpenCl core? (Not Nios) 2, If nios and other processing is involved then these needs to be included inside the opencl project, but it still need an external host to run the kernel? (http://www.alteraforum.com/forum/showthread.php?t=45791) 3, A complete opencl project can not be configured from flash running on it's own?  It is quite clear that the Altera SDK aims to use the FPGA as coprocessors, like the Microsoft data centers do, which is great, but I wish there where more info targeting standalone FPGA's.  Apus

[Altera_Forum]

I'm in similar situation to you, we want to add an OpenCL core to our design without the need for a host. Basically we want to replace a portion of our vhdl design with OpenCL, so using OpenCL to describe the logical behaviour instead of VHDL !, have yet to find out if it is possible !

[Altera_Forum]

I'm quite disappointed about the complete lack of response from Altera and the application engineers in this matter. It seem that the opencl kit is aimed at sw guys doing offloading and not for hard core hdl use. 

I can see that making rtl from opencl is not an easy task, but still.

[Altera_Forum]

Try contacting Altera or your application engineer directly, this is mostly a user forum.

[Altera_Forum]

If you want to have a mixed RTL+OpenCL solution give a look at this: https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-design-example.html