Compiling with different seeds and Aggresive optimizations

[Altera_Forum]

My compilation failed due to complex routing. 

 !=========================================================================== ! The report below may be inaccurate. A more comprehensive  ! resource usage report can be found at conv_pipe/reports/report.html  !===========================================================================   +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 83% ; ; ALUTs ; 55% ; ; Dedicated logic registers ; 34% ; ; Memory blocks ; 104% ; ; DSP blocks ; 3% ; +----------------------------------------+---------------------------; aoc: First stage compilation completed successfully. Compiling for FPGA. This process may take a long time, please be patient. High-effort hardware generation selected, compile time may increase signficantly. Error (170143): Final fitting attempt was unsuccessful Error: An error occurred during routing Error: Quartus Prime Fitter was unsuccessful. 2 errors, 81 warnings Error: The design has not been fully routed. If you want to perform Timing Analysis on an earlier netlist please choose which snapshot to load for analysis. Available snapshot(s): planned or placed snapshot. Error: Quartus Prime TimeQuest Timing Analyzer was unsuccessful. 1 error, 0 warnings Error: Quartus Fitter has failed! Breaking execution... Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 2 errors, 0 warnings Error: Compiler Error, not able to generate hardware  In the Quartus log I have   Critical Warning (188026): The Fitter failed to successfully route the design. You may be able get this design to route by making design modifications, changing the fitter seed or by enabling the fitter aggressive routability optimizations logic option. How to enable this option? I am already using -high-effort flag in aoc command.

[Altera_Forum]

Those messages are for people who use Quartus directly. You can change the seed using the --seed switch followed by an integer number but considering the high logic usage and the high possibility of overutilizing the Block RAMs, you will likely not be able to successfully compile this design unless you somehow reduce the area utilization.

[Altera_Forum]

I am currently compiling for a10gx bsp. In the HTML reports the total BRAM count is 2531. In reality the total number of BRAM blocks are 2713. Below is the top.fit.summary 

 Fitter Status : Failed - Wed Jul 4 05:35:43 2018 Quartus Prime Version : 17.1.2 Build 304 01/31/2018 SJ Pro Edition Revision Name : top Top-level Entity Name : top Family : Arria 10 Device : 10AX115S2F45I1SG Timing Models : Final Logic utilization (in ALMs) : 357,354 / 427,200 ( 84 % ) Total registers : 558818 Total pins : 173 / 960 ( 18 % ) Total virtual pins : 0 Total block memory bits : 45,919,784 / 55,562,240 ( 83 % ) Total RAM Blocks : 2,669 / 2,713 ( 98 % ) Total DSP Blocks : 1,075 / 1,518 ( 71 % ) Total HSSI RX channels : 8 / 72 ( 11 % ) Total HSSI TX channels : 8 / 72 ( 11 % ) Total PLLs : 78 / 144 ( 54 % )  So RAM is just sufficient. Do you think I should still optimize the logic utilization? If so, when could I expect succesful compilation? (what percentage of logic utilization). Because the compilation failed again.

[Altera_Forum]

On Arria 10 with the standard flow that uses partial reconfiguration, Block RAM utilization above 95% and logic utilization above 75% will very likely run into fitting or routing failure. In your case you probably need to focus on reducing the logic utilization by 5 to 10% for the design to become routable.