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Hi All,
I am relatively new to VHDL and I'm trying to implement the following actions for the related ctrl strings: --ADD when ctrl="000" else --SUB when ctrl="001" else ALUOUT <= ABUS and BBUS when ctrl="010" else ALUOUT <= ABUS or BBUS when ctrl="011" else ALUOUT <= ABUS xor BBUS when ctrl="100" else ALUOUT <= not ABUS when ctrl="101" else ALUOUT <= ABUS when ctrl="110" My problem is that I already have an adder designed in a verilog module which I am calling using component instantiation and the principle "A-B=A+(not B) + 1" for the Subtraction operation. The two component instantiations are as below: u1: NBitAdder port map(Aalu=>ABUS, Balu=>BBUS, c=>'0', sumA=>ALUOUT, carryA=>cout); u2: NBitAdder port map(Aalu=>ABUS, Balu=>not BBUS, c=>'0', sumA=>ALUOUT, carryA=>cout); But how can I implement only 1 of these depending on the ctrl inputs?? From what I understand an instantiation cannot be used within the WHEN process. Any help would be much appreciated. Thanks in advance.Link Copied
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Oops..That smiley face in my Subtraction operation should be a b.
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Your mux structure in VHDL should be a little different. Try:
--ADD when ctrl="000" else
--SUB when ctrl="001" else
ALUOUT <= (ABUS and BBUS) when ctrl="010" else
(ABUS or BBUS) when ctrl="011" else
(ABUS xor BBUS) when ctrl="100" else
(not ABUS) when ctrl="101" else
(ABUS); -- when ctrl="110"
Component instantiations need to be done outside of process statements in VHDL. You will need to create signals to connect to the two outputs and mux them appropriately. Something like the following: u1: NBitAdder
port map
(
Aalu => ABUS,
Balu => BBUS,
c => '0',
sumA => u1_sumA_out, --ALUOUT,
carryA => u1_carryA_out --cout
);
u2: NBitAdder
port map
(
Aalu => ABUS,
Balu => not BBUS,
c => '0',
sumA => u2_sumA_out, --ALUOUT,
carryA => u2_carryA_out --cout
);
ALUOUT <= u1_sumA_out WHEN (control = '1') ELSE u2_carryA_out;
cout <= u1_carryA_out WHEN (control = '1') ELSE u2_carryA_out;

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