Re: Concatenation operator in a port assignment ?

RHerm1 · ‎09-13-2019

I'm using Quartus 18.1.1 / Build 646 and have observed a strange behavior with the following VHDL code:

  meta_data_ram : altsyncram
  generic map (
   .......
  )
  port map (
    address_a => md_upper_reg & channel_inreg;
   .....
  );

The issue concerns the port "address_a": With Signal Tap I see the following values:

md_upper_reg = '1' and channel_inreg = "00000"

==> address_a is "000001" instead of "100000" as expected

When I change the code like this...

  md_wr_addr  <= md_upper_reg & channel_inreg;
 
  meta_data_ram : altsyncram
  generic map (
  ... 
  )
  port map (
    address_a => md_wr_addr,
    .........

everything works fine !!

If the compiler can't handle the concatenation operator in a port assignment I would expect that there is either an error or the signal assignment is done correctly!

Did I miss something or is this a Quartus issue?

MEIYAN_L_Intel · ‎09-17-2019

Hi,

I had found out that it might be due to the VHDL version used in Quartus.

For an example here:

In VHDL 2008:

comp_inst : comp

port map(

thing => "000" & sig

);

In VHDL 93:

tempsig <= "000" & sig;

comp_inst : comp

port map(

thing => tempsig

);

You may check your VHDL version in by clicking assignment >settings>VHDL input.

Thanks

RHerm1 · ‎09-17-2019

Thanks for your reply,

I'm using VDHL 2008 and the issue is that a wrong value is assigned to the port "address_a". When I assign the same expression to a signal first and then this signal to a port it works!!

MEIYAN_L_Intel · ‎10-01-2019

Hi,

May I know any new issue facing?

Thanks.