Config via Protocol - periphery IO default voltage levels

[Altera_Forum]

I've started using Configuration via Protocol and I can get my board periphery loaded in time for PCIE and I can get the core programmed once Linux has booted on the host. In the meantime, it would be nice to be able to hold various I/O at predetermined levels so that while the core isn't configured other components on the board can behave in a default state. 

 I'm not using the partitioned design principle as I'm using Quartus Prime Lite, so was wondering how I can persuade Quartus to default some I/O to predetermined levels in the periphery file.  Cheers, Simon

[Altera_Forum]

Hi Simon,I'm also using CvP now. My understanding is that while in CvP mode, you can't hold various I/O at predetermined levels but tri-stated. You might need external on-board resistor pair to achieve your predetermined levels. I encountered a problem that if I enable CvP and "open ("/dev/altera_cvp", O_RDWR);" and try to access BAR registers, it seems I loss control of the board. Do I need to modify the Sample CvP Linux driver?Br,aroamerer 

--- Quote Start ---  I've started using Configuration via Protocol and I can get my board periphery loaded in time for PCIE and I can get the core programmed once Linux has booted on the host. In the meantime, it would be nice to be able to hold various I/O at predetermined levels so that while the core isn't configured other components on the board can behave in a default state.I'm not using the partitioned design principle as I'm using Quartus Prime Lite, so was wondering how I can persuade Quartus to default some I/O to predetermined levels in the periphery file.Cheers,Simon  --- Quote End ---  

[Altera_Forum]

Hi aroamerer, 

If they are tri-stated I'd have thought it would work, but will check my circuit.  As regards your question, I'm not sure - I have modified the Linux driver for our own board, but the driver open, probe and close functions are largely the same. I load the driver, program the board, and then when it has finished programming test that I can read some of the FPGA registers my board has, and all is successful. The check that the programmer did on finishing programming was crashing Linux, but then it was asking to read outside of the BAR, so not too surprising. I'm using the driver source that came with an earlier release, for an Altera OpenCL board, so not sure if other drivers work similarly or not.  Cheers, Simon

[Altera_Forum]

--- Quote Start ---  Hi aroamerer, If they are tri-stated I'd have thought it would work, but will check my circuit.  As regards your question, I'm not sure - I have modified the Linux driver for our own board, but the driver open, probe and close functions are largely the same. I load the driver, program the board, and then when it has finished programming test that I can read some of the FPGA registers my board has, and all is successful. The check that the programmer did on finishing programming was crashing Linux, but then it was asking to read outside of the BAR, so not too surprising. I'm using the driver source that came with an earlier release, for an Altera OpenCL board, so not sure if other drivers work similarly or not.  Cheers, Simon  --- Quote End ---    Hi Simon,   Thanks for your quick reply.   I've found a way to walk arround. I use DMA sample driver instead of CVP driver. It works fine when I open the device. Later I will check the difference. At least I know there is something wrong with the driver instead of FPGA settings.   Br, aroamerer

[Altera_Forum]

--- Quote Start ---   My understanding is that while in CvP mode, you can't hold various I/O at predetermined levels but tri-stated.   --- Quote End ---    Do you have any idea where this is documented? I haven't been able to find it in the UG for CvP or the Arria10 handbook. Thanks.

[Altera_Forum]

--- Quote Start ---  Do you have any idea where this is documented? I haven't been able to find it in the UG for CvP or the Arria10 handbook. Thanks.  --- Quote End ---    The document I read is "Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide(UG-01101,2015.11.02)".