Configuring PCIe MSI

[Altera_Forum]

I've implemented a PCIe design in Qsys. 

 I'm confused about configuring the MSI capability structure. My understanding is that the host driver must configure all or part of these registers, which are located at 0x050 (page 6-3, table 6-4) in the common configuration space header.  But in the Avalon-MM Bridge register map (p. 6-7 table 6-12) there is an interrupt enable register at address 0x050. This address space is accessed through the CRA slave port.  So these must be 2 different address spaces. My driver can access the CRA registers through a BAR and read/write values.  But how am I supposed to access the MSI capability structure? References above are to 'IP compiler for PCIe User guide'. It's unclear whether the MSI capability structure is partly populated automatically (is a capability ID of 05 automatically generated?) And if not, then how can I access this address space if not via the CRA port?

[Altera_Forum]

--- Quote Start ---  I've implemented a PCIe design in Qsys. I'm confused about configuring the MSI capability structure. My understanding is that the host driver must configure all or part of these registers, which are located at 0x050 (page 6-3, table 6-4) in the common configuration space header.   But in the Avalon-MM Bridge register map (p. 6-7 table 6-12) there is an interrupt enable register at address 0x050. This address space is accessed through the CRA slave port.   So these must be 2 different address spaces. My driver can access the CRA registers through a BAR and read/write values.   But how am I supposed to access the MSI capability structure? References above are to 'IP compiler for PCIe User guide'. It's unclear whether the MSI capability structure is partly populated automatically (is a capability ID of 05 automatically generated?) And if not, then how can I access this address space if not via the CRA port?  --- Quote End ---       I have used legacy interrupts so don't think I had to worrk about capability IDs and can't answer your question.   A word of warning though, legacy interrupts were broken in Q11.0 and the 11.1 sp2 DMA engine was introducing holes in data transferred (that was workign in 11.0).    I'd recommend Q 12.0, it seems to be doing what it should (so far).   Nial