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I'm creating a design for Arria 10 that uses the Bitec HDMI IP to receive and transmit video + auxilliary data. A Bitec HDMI input output board is connected to an ReflexCES ALARIC development board via an FMC connector. Video lines use the high speed transceiver, but auxilliary data is transmitted via LVDS pins as i2c. My question is, how do I initialize these pins properly to work as i2c pins.
My input/output parameter in the top Verilog design are: output hdmi_rx_hpd_n, inout hdmi_rx_i2c_sda, input hdmi_rx_i2c_scl, input hdmi_tx_hpd_n, inout hdmi_tx_i2c_sda, inout hdmi_tx_i2c_scl Pin characteristics are: I/O Standard, 1.5V Pins used are: AM6, AM5, AP9, AH10, AH9, AJ7 Quartus analysis and synthesis works alright, but when running the fitter I get the following error: Error (11924): Bank '3A' has conflicting VCCIO settings Error (11928): 'hdmi_rx_hpd_n' with I/O standard 1.5 V, was constrained to be within bank '3A' Info (11929): '1.5V' is a valid VCCIO value Error (11928): 'fmc_clk_dir' with I/O standard 1.8 V, was constrained to be within bank '3A' Info (11929): '1.8V' is a valid VCCIO value Error (16297): An error has occurred while trying to initialize the plan stage. I'm using Quartus 15.1 Standard, no patch. Any idea, what I did wrong? KlausLink Copied
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At a guess, you've got hdmi_rx_hpd_n set as I/O standard 1.5V and fmc_clk_dir set as IO standard 1.8V, and they're both in the same bank 3A. What is your VCCIO voltage set to for this bank?
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--- Quote Start --- At a guess, you've got hdmi_rx_hpd_n set as I/O standard 1.5V and fmc_clk_dir set as IO standard 1.8V, and they're both in the same bank 3A. What is your VCCIO voltage set to for this bank? --- Quote End --- You are absolutely right. I'm using a mix of two reference designs (ReflexCES's and Bitec's) and got a lot of pin assignments mixed up, as I'm relatively new to this. I have reduced my pin-count to only the necessary ones now and fixed the VCCIO settings. I'm using default 1.8V VCCIO for all HDMI i2c pins. Thank you!

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