Connect an output port to an input port from different entities

Altera_Forum · ‎03-25-2015

I'm trying to write a code that shifts the LED light from LEDR0 to LEDR1, then from LEDR1 to LEDR2 and all the way up to LEDR9 then back to LEDR0 with 1 second interval on each LED.

I've implemented the entity instantiation by writing three entities. The first entity is where it generates 1 second clock from on-board 50MHz clock. The second entity uses the 1 second clock from the first entity and shifts the LED light from LEDR0 to LEDR9 non-stop unless the reset button (KEY0) is pressed, then it will start from the beginning (LEDR0) and works its way up to LEDR9 again. The last entity is the top entity where all the ports are connected to the physical pins on my DE1-SoC board.

frist entity: 1 second clock

library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Clock_1_sub is
    port(
        -- Input ports
        clk_50    : in  std_logic;
        
        -- Output ports
        clk_01    : out std_logic
    );
end Clock_1_sub;
architecture Clock_1_structure_sub of Clock_1_sub is
    signal clk_signal : std_logic := '0';
    
begin
    process(clk_50) is 
        variable count : integer := 1; 
    begin 
        if(clk_50'event and clk_50='1') then 
            count := count + 1;
            if (count = 25000000) then
                clk_signal <= not clk_signal;
                count := 1;
            end if;
        end if;
    end process;
    clk_01 <= clk_signal;
end Clock_1_structure_sub;

second entity: shifting led

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RotateLED_sub is
    port(
        -- Input ports
        reset        : in  std_logic;
        clk_1sec    : in  std_logic;
        -- Output ports
        light        : out std_logic_vector(9 downto 0)
    );
end RotateLED_sub;
architecture RotateLED_structure_sub of RotateLED_sub is
    signal shift : std_logic_vector(9 downto 0) := "0000000001";
begin
    OneSecondClock: entity work.Clock_1_sub(Clock_1_structure_sub)
    port map (
        clk_01 => clk_1sec  --**************ERROR HERE******************
    );
    light <= shift;
    
    process(reset, clk_1sec) is 
    begin 
        if(reset = '1') then
            shift <= "0000000001";
        elsif(rising_edge(clk_1sec)) then
            shift <= shift(0) & shift(9 downto 1);
        end if;
    end process;     
    
end RotateLED_structure_sub;

third entity: top entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ShiftWithClk_top is
    port(
        KEY        : in  std_logic;
        CLOCK_50    : in  std_logic;
        LEDR        : out std_logic_vector(9 downto 0)
    );
end ShiftWithClk_top;
architecture ShiftWithClk_structure of ShiftWithClk_top is
begin
    level_1: ENTITY work.RotateLED_sub (RotateLED_structure_sub) port map(
    reset => KEY,
    clk_1sec => CLOCK_50, 
    light => LEDR
    );
end ShiftWithClk_structure;

My question is that Quartus is complaining about the line where I map the output port "clk_01" generated from the first entity to the input port "clk_1sec" in my second entity. Are there any other ways to properly connect an output port to an input port in different entities?

Altera_Forum · ‎03-25-2015

In your code, you havent instantiated the clock_1_sub entity. so there is no mapping possible.

To map between entities, you need signals (like wires on a PCB) to carry the signal between the entities.

Altera_Forum · ‎03-25-2015

You cannot connect an input to an output. Think of it like wires on a PCB.

You need to connect an input to an input, and an output to an output.

Altera_Forum · ‎03-25-2015

Thank you guys! Now I know I can't connect an output port to an input port.

I've instantiated the clock_1_sub in my top-level entity and also created a new signal for the connection between those I/O ports and it's now working fine :D