Connecting DDR3 on ArriaII GX Development Kit

[Altera_Forum]

Hello, 

My design has an DDR3-Interface. Pin Assignment I copied from Referencedesign "a2gx125_qsys_pcie_gen1x4_11_0_1". Fitter Works successfully, but I get a Critical Warning. Can anyone help? Thank you in advance  Critical Warning (185021):  Detected external clock signal directly connected to the RAM "q_sys: u0|q_sys_cpu:cpu|q_sys_cpu_nios2_oci: the_q_sys_cpu_nios2_oci|q_sys_cpu_nios2_ocimem: the_q_sys_cpu_nios2_ocimem|q_sys_cpu_ociram_lpm_dram_bdp_component_module: q_sys_cpu_ociram_lpm_dram_bdp_component|altsyncram: the_altsyncram|altsyncram_14e2:auto_generated|q_a[0]" CLK0 port.  This connection may cause unexpected memory behavior if your external clock signal violates  the minimum pulse width specifications (clock high time and clock low time).

[Altera_Forum]

Using Quartus II 12.0. Same error with Stratix IV / DDR2 Controller 

 Project is from terasic QSYS 11.0 DDR2 Example. I only added a PCIe IP Core. The DDR2 Controller has an 50 MHz(OSC_50_Bank3) input clock, no PLL. :(  Found on: quartushelp[.]atlera[.]com  ACTION: Use the on-chip phase-locked loop (PLL) as the input clock source to the memory block.  Strange. The example from terasic (DE4_DDR2_UniPHY) does not use a PLL as an input clock and it works without critical errors. why?  Edit: Still doesn't work with PLL. :confused: