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Hello,
Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3FFF_FFFF. Now, when I try to connect another device to the HPS (over the same H2F_AXI_MASTER) - I get an address contention. Using higher addresses generates the following error message: --- Quote Start --- Error: qsys.hps.h2f_axi_master: outside the master's address range (0x0..0x3fffffff) --- Quote End --- What is the address width of the H2F_AXI_MASTER bus ?Link Copied
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See the address map in the documentation:
https://www.altera.com/hps/en_us/cyclone-v/hps.html#topic/sfo1418687413697.html- Mark as New
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I can't find an element in the table that corresponds to the 0x0000_0000 - 0x3FFF_FFFF address range indicated by Qsys.
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The first row in the table is The H2F_AXI_MASTER bus that you are inquiring about.
The addresses shown are from the ARM perspective. The addresses within Qsys are from the FPGA perspective.- Mark as New
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So for example:
1. If the HPS writes to its address 0xC000_0000 the data will appear in whatever is connected to address 0x0000_0000 on the FPGA ? 2. If the HPS writes to its address 0xC000_1000 the data will appear in whatever is connected to address 0x0000_1000 on the FPGA ?- Mark as New
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Yes, 0xC0000000 is the fixed base address of the FPGA subsystem components accessed by the H2F_AXI_MASTER.
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