Hello,Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3FFF_FFFF. Now, when I try to connect another device to the HPS (over the same H2F_AXI_MASTER) - I get an address contention. Using higher addresses generates the following error message: --- Quote Start --- Error: qsys.hps.h2f_axi_master: outside the master's address range (0x0..0x3fffffff) --- Quote End --- What is the address width of the H2F_AXI_MASTER bus ?
The first row in the table is The H2F_AXI_MASTER bus that you are inquiring about.The addresses shown are from the ARM perspective. The addresses within Qsys are from the FPGA perspective.
So for example:1. If the HPS writes to its address 0xC000_0000 the data will appear in whatever is connected to address 0x0000_0000 on the FPGA ? 2. If the HPS writes to its address 0xC000_1000 the data will appear in whatever is connected to address 0x0000_1000 on the FPGA ?