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Altera_Forum
Honored Contributor I
1,064 Views

Connecting HPS to FPGA DDR3 takes up all the address space

Hello, 

 

Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. 

The DDR3 Controller is assigned address: 0x0000_0000 to 0x3FFF_FFFF. 

 

Now, when I try to connect another device to the HPS (over the same H2F_AXI_MASTER) - I get an address contention. 

Using higher addresses generates the following error message: 

 

 

--- Quote Start ---  

Error: qsys.hps.h2f_axi_master: outside the master's address range (0x0..0x3fffffff) 

 

--- Quote End ---  

 

What is the address width of the H2F_AXI_MASTER bus ?
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5 Replies
Altera_Forum
Honored Contributor I
35 Views

Altera_Forum
Honored Contributor I
35 Views

I can't find an element in the table that corresponds to the 0x0000_0000 - 0x3FFF_FFFF address range indicated by Qsys.

Altera_Forum
Honored Contributor I
35 Views

The first row in the table is The H2F_AXI_MASTER bus that you are inquiring about. 

The addresses shown are from the ARM perspective. 

The addresses within Qsys are from the FPGA perspective.
Altera_Forum
Honored Contributor I
35 Views

So for example: 

1. If the HPS writes to its address 0xC000_0000 the data will appear in whatever is connected to address 0x0000_0000 on the FPGA ?  

2. If the HPS writes to its address 0xC000_1000 the data will appear in whatever is connected to address 0x0000_1000 on the FPGA ?
Altera_Forum
Honored Contributor I
35 Views

Yes, 0xC0000000 is the fixed base address of the FPGA subsystem components accessed by the H2F_AXI_MASTER.

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