Constrain DDR2 IP -- need help

[Altera_Forum]

Hi, 

 I need your help for constrain my design based on the DDR2 HP IP from Altera.  Actualy, I'm really a newbie in this particular step. I never have manually constrain a design.  Well, my design is composed of one ddr2 controller (generated by megawizard), one logical block to write some patterns in ddr2 memory and another logical block to read out theses patterns (please see attached images to view a screenshot of my top level project).  Altera provide a sdc file for constrain ddr2 ip. So I use it and add some constraints on my inputs and my logic (reset_n, start_write and start_read inputs and led) (please see attached file to view the complete sdc file I use).  The design works good on real board (Stratix II GX PCI Expres development board) but during compilation, I have some timing issues. I have a minimum pulse width violations. First, i say : "it's nothing. All works fine".  But later, when I wanted to re-use this design in another working design (composed by an ethernet mac, a nios II processor and some other logic). and when I add all together, I have got many timing issues and nothing works properly...  So in a first time, I would like to fix my ddr2 design correctly.  So please, could you tell me why I've got a minimum pulse with timing error ? What can I do to fix it ?  Have you some links for learning basics about timing constraining ? (I will read the section 3 of quartus handbook, i think it will be usefull!)  Thanks in advance! See you.  Fabrice.

[Altera_Forum]

The "Minimum Pulse Width" violation with type "Port Rate" for mem_addr[11] means that the actual toggle rate based on the 3 ns actual width is too fast relative to the 3.018 ns required width for the combination of I/O standard and drive strength. (The specs for toggle rate for each I/O standard are in the device handbook.) 

 Do you have something different shown in the Assignment Editor for this one device pin compared to the other mem_addr[*] pins, which have a 2.708 ns required width?  When you generated the DDR2 MegaCore, you should have gotten generation messages that told you to run a .tcl script to set up the assignments like I/O standard.

[Altera_Forum]

Hi, 

 Ok. Thank you Brad for reply. I will check all my assignments, especially for the mem_addr bus and mem_addr[11]. Maybe something goes wrong here!  Another question: you say that the specifications for toggle rate for each I/O standard are in the device handbook. But I have search in the stratix II gx handbook and I didn't found them ?!  Could you tell me in which chapter / section have you find theses informations. Thanks you very much.  I will keep you inform for my problem. See you.  Fabrice.

[Altera_Forum]

--- Quote Start ---  Another question: you say that the specifications for toggle rate for each I/O standard are in the device handbook. But I have search in the stratix II gx handbook and I didn't found them ?!  Could you tell me in which chapter / section have you find theses informations.  --- Quote End ---     Volume 1, Section I, Chapter 4, under "Maximum Input and Output Clock Toggle Rate". Find the correct table for output clock rate (these tables apply to outputs with regular data signals, not just clocks), change the stated frequency to period with picosecond resolution, and adjust by the derating factor in Table 4-97.

[Altera_Forum]

Up! 

 Bad news (for me!).  All my assignments seems to be ok and all pins of the mem_addr bus have the same assignments (exactly the same).   mem_addr [*] :I/Os standard : SSTL-18 Class I Current strength : Maximal current Output Pin Load : 10 pF   I use PCI Express dev board with stratixx II GX. Interface between DDR2 and FPGA don't use ODT but external terminations. So the tcl script generated by the mega wizard is not good for my board (because it use ODT functionnality)  In the AN328, I found an example of implementation of DDR2 HP IP on the same board I use. (http://www.altera.com/literature/an/an328.pdf)  So I follow all the application note recommandations for applying constraints (see AN328 page 36/37/38). And the result, after compilation is the same as before.... => minimum pulse width error on mem_addr[11]  The only thing I notice is that mem_addr[11] is on the clk5n out pin and others mem_addr [*] pins are on standard out pin (B8_IOxx). Is that important or not ?? Does I apply some specific constraints because of the clk5n pin ?  Do you want I post my entire project in order to help you to resolve my issues ?  Thanks in advance for your help!

[Altera_Forum]

The timing can be different for special pins, so the CLK5n pin seems like the likely explanation for mem_addr[11] having a different port rate spec. You might be able to confirm this in the device handbook. 

 Because you are stuck with the pin that was already wired up on the development board, there might be nothing you can do to make it run faster. If you are not using the highest available drive strength, you could try increasing the drive strength. I wouldn't bother though. Your violation was only 18 ps, so you should be OK for actual operation unless your board just happens to have a device at the slow end of the process extreme (unlikely) and you are running your board at the slow ends of the supply voltage and temperature extremes (seems unlikely for use of a development board).

[Altera_Forum]

Hi brad, 

 Thanks for all your hints. You're right, 18 ps in the worst case is not relevant for my application. But I wish fix that just for learning how to identify and resolve some timing errors. Just for playing with sdc files and timequest analyser.  I have check in the device handbook specification for my specific io pin (assigned for mem_addr[11]) and with its clock rate and derating factor, I'm able to retreive required pulse width (3.018 ns).  This is because it's a dedicated output clock pin. For all others pins interfacing with DDR (using standard I/O pin), the minimum pulse width is 2.718 ns.  It's really strange because a dedicated output clock can not run faster than a simple standard output pin... ?!  So, before closing the subject, is there some special constraints I can apply on my mem_addr[11] pin to pass all my timing requirements ?? (I don't think so...)  Now, my simple DDR2 design is fully constraint, so I will try to make the same with my TSE - NIOS II - DDR2 design... !  I will come back later if I have more questions about timing contraints. And yet one time, thank you very much for your answers and your rapidity.  Se you!

[Altera_Forum]

--- Quote Start ---  ... is there some special constraints I can apply on my mem_addr[11] pin to pass all my timing requirements ?? (I don't think so...)  --- Quote End ---    You can't change the device's maximum toggle rate limit for your combination of I/O settings for pin location, I/O standard, drive strength, slew rate, and on-chip termination (not all devices have all these kinds of assignments). If you need the pin to be able to toggle faster, you need to change one of those things.  The constraints tell TimeQuest how fast the pin might toggle. You need the constraints to match the actual design behavior. If the pin really might toggle as fast as TimeQuest thinks based on the clock related to this data output, then changing the timing constraints is not a valid solution. There might be some trick you could do with SDC constraints if the data signal won't be toggling as fast as possible given the clock frequency of the register driving the pin, but the only thing that comes to mind (except maybe something with a multicycle exception) would make other things in the timing be constrained incorrectly. There are toggle-rate settings visible in the Assignment Editor and stored in the .qsf for other purposes (at least for certain device families), but I doubt that there is one used by TimeQuest (almost everything TimeQuest uses comes from .sdc files, not the .qsf).