Constraining a source synchronous, SDR, center aligned Input

[Altera_Forum]

I'm running mad with this: 

 I want to connect a Texas Instruments TLK2201 to my FPGA (Cyclone IV). This Ethernet-Serdes has got a Ten-Bit-Interface (TBI) with center aligned Data at 125MHz. The Data are valid on the rising edge of the clock. If I look at the Data and Clock directly on the board, all Data are changing at the same time and the rising edge of the clock is exactly in the middle of two Data-changes. But when I watch the TBI inside the FPGA via Logic Analyzer Interface (LAI) the Data-changes on the ten Signals varies by 2 to 3 ns. And both clock edges are so close to the Data-changes that it is nearly impossible to get some valid Data either on the rising nor the falling Edge.  I tried a lot on constraining the Input-Delays, but all the examples are confusing me more than give me a hint what to do next. I tried the Assistant for source-synchronous-Inputs (quartus_sta --ssc), I tried to constrain it by the example given here: http://www.altera.com/support/examples/timequest/exm-tq-ca_ss_in.html but what the heck is that "data-clock". I don't see why I have to constain a PLL tha isn't in the design of my FPGA. And another example created a virtual clock with "create_generated_clock". Aren't virtual clocks not constrained by "create_clock"???? See: http://www.alteraforum.com/forum/showthread.php?t=35273&highlight=constrain+sdr+center+aligned And I read the AN433 forward AND backward without getting a single clue out of it. Sometimes my constrains seem to work, sometimes they don't. But everything I see is really none deterministic. I just don't get it!!  How can I constrain the Data Inputs to change at the same time? How can I just get the clock center aligned into my design so I can read the Data on the falling edge of this clock?  Pleeeease I need Help or at least a psychiatrist.  Just tell me, what you want to know about my Design and I will provide it to you as soon as possible.  Thanks to you all  Yours Steffen

[Altera_Forum]

--- Quote Start ---  I'm running mad with this:  I want to connect a Texas Instruments TLK2201 to my FPGA (Cyclone IV). This Ethernet-Serdes has got a Ten-Bit-Interface (TBI) with center aligned Data at 125MHz. The Data are valid on the rising edge of the clock. If I look at the Data and Clock directly on the board, all Data are changing at the same time and the rising edge of the clock is exactly in the middle of two Data-changes. But when I watch the TBI inside the FPGA via Logic Analyzer Interface (LAI) the Data-changes on the ten Signals varies by 2 to 3 ns. And both clock edges are so close to the Data-changes that it is nearly impossible to get some valid Data either on the rising nor the falling Edge.  I tried a lot on constraining the Input-Delays, but all the examples are confusing me more than give me a hint what to do next. I tried the Assistant for source-synchronous-Inputs (quartus_sta --ssc), I tried to constrain it by the example given here: http://www.altera.com/support/examples/timequest/exm-tq-ca_ss_in.html but what the heck is that "data-clock". I don't see why I have to constain a PLL tha isn't in the design of my FPGA. And another example created a virtual clock with "create_generated_clock". Aren't virtual clocks not constrained by "create_clock"???? See: http://www.alteraforum.com/forum/showthread.php?t=35273&highlight=constrain+sdr+center+aligned And I read the AN433 forward AND backward without getting a single clue out of it. Sometimes my constrains seem to work, sometimes they don't. But everything I see is really none deterministic. I just don't get it!!  How can I constrain the Data Inputs to change at the same time? How can I just get the clock center aligned into my design so I can read the Data on the falling edge of this clock?  Pleeeease I need Help or at least a psychiatrist.  Just tell me, what you want to know about my Design and I will provide it to you as soon as possible.  Thanks to you all  Yours Steffen  --- Quote End ---    I certainly feel your frustration with some TimeQuest examples. To cut it short I will approach any input case with the same basic principle that input max delay/min delay are just information about "data offset from its clock as received at fpga pins".  Thus if data eye is aligned centred on rising clock edge and since you can measure it then find out tCO min and tCO max i.e. the window that follows valid data(first x and last x below):  ----|----------------|--- <--valid--> xxxx <--valid-->  Then enter that as set max/min delay for inputs. If timing passes then I wouldn't worry about skew inside fpga.

[Altera_Forum]

OK, I tried this. With no effect.  

 Now I'm trying something totally different: I implemented a PLL into the received clock and set it to source synchronous mode. Then I set the Input-Pins in the assignment editor to PLL compensated and also set them to "Input Delay from Pin to Input Register" = 0. This is described in the Device Handbook for cyclone IV in Chapter 5 "Source-Synchronous Mode".  Now I finally have full control over the received clock to move it where I want. But I also have this warning:  Warning (176264): Can't pack I/O cell SERDES_RD[4]~input -- no fan-out from combinational output port Quartus Help told me that I have enabled the "Fast Input Register"-Option in the Assignment Editor. NO, I HAVEN'T. I also tried to set "Fast Input Register" to Off in the Assignment-Editor. But the warning didn't disappear. When I remove the "Input Delay from Pin to Input Register"-Option, the warning disappears. BUT: The Fitter always tells me that the PLL Compensation Assignment is ignored. Is there something more I have to do? Like some global setting?  In the SDC-File I tried to set the maximum skew of the Inputs with: set_max_skew -from [get_ports {SERDES_RD [*]}] -to * 0.100 (And some other Values) All with the same effect: the skew seems to be stucked at about 1.5ns. I don't get it. Do some of the constraints have to be enabled somewhere? Are they overwritten by some other setting?

[Altera_Forum]

Hmmmmm, I just read "AN 251: Using PLLs in Cyclone Devices" 

There is no word, that source-synchronous mode is supported by cyclone devices. Is this the reason for the warnings? Can someone verify?

[Altera_Forum]

--- Quote Start ---  OK, I tried this. With no effect.     --- Quote End ---    do you mean it did not pass timing or you are not happy with fpga skew? If it passes timing then you got no problem. If it didn't then you may resort to PLL but a speed of 125MHz(SDR) should not a problem I believe.

[Altera_Forum]

The only way for me to have a look on the received Signals inside the FPGA is the Logic-Analyzer-Interface (LAI). 

It always showed me, that the data are almost edge-aligned to the clock. I meassured the Bus-Signals on the Ethernet-Serdes and they were proberly center-aligned. I then wathed the Output of my 8b10b-Decoder and often it decoded Data where no Data was sent. It also had a weird behaviour on it's control-signals (It decodes K28.5 to an IDLE-Signal).  Since I use the way with the PLL everything works fine and I can finally adjust the rising edge of the Clock to the Center of the Data. So I will stay on this solution.   But now I have a little Problem: The Fitter always shows me this warning: Warning (15062): PLL "<MY_PLL>" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register  I set the Input-Pins (or Ports) to "PLL compensated" in the assignment editor. But how do I finally connect the Output of the PLL to them? I thought this is made automatically.

[Altera_Forum]

OK, I think I got it: 

The Input Pins have to be set to "Fast Input Register". Right?

[Altera_Forum]

This all just don't work!!:mad: 

 The good news is that I found an error in my design: The Component which receives the data had an asynchronous reset which preventet the inputs from using fast IO registers. => I didn't really need that reset so I deleted it.  Well, I tried a lot now: I think the best way must be a PLL in the receiving clock set to Source-Synchronous mode. The Input Pins are set to PLL-Compensated and "Input to Register Delay"-Option is set to 0. Like it is described here: http://www.altera.com/support/kdb/solutions/rd04042007_404.html  But when I receive some data over this, I get a lot of errors. When I look at the Inputs of the first component which receives the Data (via LAI), there Is a huge skew in the Datas (about 2ns). Why is there such a skew?  I tried to set up a set_max_skew constraint to the Inputs, but all the fitter sais is that it can't find a matching port/keeper/whatever.  And on top of that I have the suspicion that some busses WITHIN my design also have a skew. (Perhaps the data are already send incorrectly)  Is there a need/way to constrain busses within the fpga with set_max_skew?