Constraining registered and combinational path independent of each other

[Altera_Forum]

Hello, 

 I have a small CPLD project where one pin is connected to a register and also to some combinational logic, similar to the following code:  library ieee; use ieee.std_logic_1164.all;  entity test_max_delay is  port (  CPU_WE : in std_logic;  CPU_CLK : in std_logic;  WE_comb : out std_logic;  WE_reg : out std_logic  ); end entity test_max_delay;  architecture synthesis of test_max_delay is begin  Reg : process (CPU_CLK) is  begin  if rising_edge(CPU_CLK) then  WE_reg <= CPU_WE;  end if;  end process Reg;   WE_comb <= CPU_WE;  end architecture synthesis;  Now I want to set up all three types of timing constraints: - Input setup & hold of CPU_WE relative to CPU_CLK - Clock to output for WE_reg - Propagation delay from CPU_WE to WE_reg  When using the following constraints...  set_time_format -unit ns -decimal_places 3 create_clock -name CPU_CLK -period 10.000 -waveform { 0.000 5.000 } [get_ports CPU_CLK]  set_input_delay -max 7.5ns -clock "CPU_CLK" "CPU_WE" set_input_delay -min 1.0ns -clock "CPU_CLK" "CPU_WE" set_output_delay -clock "CPU_CLK" -max 2ns "WE_reg" set_output_delay -clock "CPU_CLK" -min 0ns "WE_reg" set_max_delay -from CPU_WE -to WE_comb 6ns set_min_delay -from CPU_WE -to WE_comb 0ns  ...the input setup constraint from the registered path seems to be added to the actual propagation delay of the combinational path, i.e. input setup constraint: 7.5ns propagation delay constraint: 6.0ns actual propagation delay (CPU_WE to WE_comb): 4.631 Resulting slack: 6.0ns - (7.5ns + 4.631ns) = -6.131ns  Is there any way to constrain the combinational path completely independent of the registered path or is there any reason why the input delay is added?

[Altera_Forum]

If the starting point (CPU_WE) has a clocked delay (7.5 ns), then it will be added to the path.  

Same thing for ending points.  I don't really know why, but that's how set_max/min_delay are defined to work. There's probably a good reason..  And you can't just set_false_path -from [get_clock CPU_CLK] -to [get_ports WE_comb] because it will simply cut the path from CPU_WE to WE_comb.  What you can do is add the 7.5 ns to your max delay constraint. Ie, set_max_delay -from CPU_WE -to WE_comb 13.5ns