How to prevent QII inferring RAM

Altera_Forum · ‎04-17-2012

Hi there,

I have an array of registers that are 32 bit wide and need to be accessed in a different clock domain. So I wrote a process to cross those registers to the new clock domain by double-registering them:


   cross_registers: process (rst, clk)
   begin
      if rst = '1' then
         cnt_s                   <= (others => (others => '0'));
      elsif rising_edge(clk) then
         cnt_s                   <= cnt_s(0) & cnt;
         new_cnt               <= cnt_s(1);
      end if;
   end process cross_registers;

QII infers RAM in the implementation of this and defeated the purpose. So I added the following lines to prevent QII from doing this but to no avail.

attribute ramstyle : string;

attribute ramstyle of cnt_s : signal is "logic";

Any suggestions?

Thanks,

Hua

Altera_Forum · ‎04-17-2012

On a side note, I am not too sure about the code snippets above to be the proper way of crossing clock domain boundaries for vectors or arrays of vectors, I am thinking about the following is better, how do you think?


   cross_registers: process (rst, clk)
   begin
      if rst = '1' then
         cnt_s                   <= (others => (others => '0'));
      elsif rising_edge(clk) then
         cnt_s                   <= cnt_s(0) & cnt;
         if cnt_s(0) = cnt_s(1) then
            new_cnt            <= cnt_s(1);
         end if;
      end if;
   end process cross_registers;

Altera_Forum · ‎04-18-2012

Doubling registering arrays will work to cross the boundary, but a FIFO would be more reliable.

You'll probably fnd quartus isnt infering a RAM, its infering an ALTSHIFTTAPS megafunction, which will use RAM, because all you have is a shift register.

Altera_Forum · ‎04-18-2012

--- Quote Start ---

Doubling registering arrays will work to cross the boundary, but a FIFO would be more reliable.

You'll probably fnd quartus isnt infering a RAM, its infering an ALTSHIFTTAPS megafunction, which will use RAM, because all you have is a shift register.

--- Quote End ---

Yeah, it was a memory block in the Altshifttaps megafunction (stratix iv) and it gave timing violations. I will use fifos instead.

Thanks!

Altera_Forum · ‎04-18-2012

Are the clock domains asynchronous?

If they are not asynchronous, then there's no need for double registering -- and what Quartus did will work, assuming you've constrained them properly and TimeQuest gives a green flag.

If they are asynchronous, you need to set a false path exception so Quartus will recognize them as synchronizers..

Altera_Forum · ‎04-18-2012

Yeah they are asynchronous. And instead of using fifos, I probably end up generating flag to indicate change of value, cross the flags over to the other side, and then latch them on the flag.