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Honored Contributor I
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Conversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"

Hello everyone! 

 

I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Pong P.Chu ), since I'm not such a good programmer I decided to do it first from 0 to 9, so I wanted to try it with this code here: 

 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity BCD_Increm is Port ( i : in STD_LOGIC; -- using it as a pushbutton to increment the counting unit : out STD_LOGIC_VECTOR(3 DOWNTO 0)); end BCD_Increm; architecture BCD_arch of BCD_Incr is signal un : integer; signal u : std_logic_vector(3 downto 0); signal usi : signed (3 downto 0); begin un<='0'; -- starts with 'units' in 0's unit <= u; process(i,un) begin if (i=1) then -- check if pushbutton is 'on' if (un <= 9) then -- check if units is less than or equal to 9 un <= un + 1; -- if so, then add 1 to units usi <= to_signed(un,4); -- convert to signed u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector else un <= 0; -- if units is greater than 9 then units are 0 usi <= to_signed(un,4); -- convert to signed u <= std_logic_vector(usi(3 downto 0)); -- convert to std_logic_vector end if; else un <= un; --if pushbutton is not 'on' then keep the same value for units usi <= to_signed(un,4); -- convert to signed u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector end if; end process; end BCD_arch;  

 

I understand that it can be done with a delay but since this excercise is supposed to be done with things we hhave seen in class and until this chapter we hadn't seen delays/clocks this is why I came up with the pushbutton idea, the problem I'm having is that when I try to compile it, Xilinx ISE (I'm using Xilinx ISE for programming and the Basys2 board) gives me this errors: 

 

 

--- Quote Start ---  

Line 47. Undefined symbol 'to_signed'. Line 47. to_signed: Undefined symbol (last report in this block) Line 48. usi: Undefined symbol (last report in this block)  

--- Quote End ---  

 

 

I don't understand why is this, I already tried with "conv_signed" but it is the same result, can someone help me and let me know where am I wrong? Thanks
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4 Replies
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Honored Contributor I
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Can't see anything wrong with that code. Is it a particularly old version of ise? Btw, this is an altera forum, ise is a xilinx product (altera competitor). 

 

Elsewhere there are issues. You're missing using from the sensitive list. And your code creates a latch because your asynchronous circuit stores a value when I isn't 1. These are undesirable in FPGAs. 

 

Finally, you have an adder on un. This will not work as it will try and increment in 0 time infinitely. You need a clock to run a counter.
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Honored Contributor I
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--- Quote Start ---  

Can't see anything wrong with that code. Is it a particularly old version of ise? Btw, this is an altera forum, ise is a xilinx product (altera competitor). 

 

Elsewhere there are issues. You're missing using from the sensitive list. And your code creates a latch because your asynchronous circuit stores a value when I isn't 1. These are undesirable in FPGAs. 

 

Finally, you have an adder on un. This will not work as it will try and increment in 0 time infinitely. You need a clock to run a counter. 

--- Quote End ---  

 

 

Thanks for your answer, and I'm terribly sorry for my mistake, I just googled forums about VHDL programing and since I remembered professor said something about Altera so I signed in here, but it won't happen again :oops:. 

 

About the code, the version I'm working with is the new one, so as I understood, I must write 'usi' in the sensitive list, too, right? I'm still a little confuse about the adder situation here, and since we are not allow to use something we haven't seen in the chapter that's why I didn't make it with a clock, but I'll try it anyway, thanks
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Honored Contributor I
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Hi x_ao28, 

 

I have noticed these with your code: 

 

--- Quote Start ---  

 

signal un : integer; 

un<='0'; -- starts with 'units' in 0's 

 

--- Quote End ---  

 

you declared un as an integer but assigned a bit to it. I think you should remove the single quotation marks around the 0

 

 

--- Quote Start ---  

if (un <= 9) then -- check if units is less than or equal to 9 

--- Quote End ---  

 

I think this should be if (un = 9) then -- check if units is less than or equal to 9 

 

Add use ieee.std_logic_signed.all; along with what you have and recompile and let's get the feedback.
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Highlighted
Honored Contributor I
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--- Quote Start ---  

 

Add use ieee.std_logic_signed.all; along with what you have and recompile and let's get the feedback. 

--- Quote End ---  

 

 

Dont do this - because std_logic_signed is not a standard VHDL library. 

You should use numeric_std for arithmatic (as the OP has done).
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