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Hello,
I have been trying to convert a signal of 'sfixed' data type into signal of 'real' data type. I am using 'to_real' function. I know that real data type can not be synthesized on FPGA. I just want to check my result on ModelSim. Therefore, I just use "Analysis and Elaboration" option for compilation of my project. The problem is that when I compile it, I receive an error that "Unsupported feature: cannot synthesize non constant real objects or values"..So, can you please tell me where I am making the mistake? or what is true way to convert sfixed num to real??Link Copied
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--- Quote Start --- Hello, I have been trying to convert a signal of 'sfixed' data type into signal of 'real' data type. I am using 'to_real' function. I know that real data type can not be synthesized on FPGA. I just want to check my result on ModelSim. Therefore, I just use "Analysis and Elaboration" option for compilation of my project. The problem is that when I compile it, I receive an error that "Unsupported feature: cannot synthesize non constant real objects or values"..So, can you please tell me where I am making the mistake? or what is true way to convert sfixed num to real?? --- Quote End --- You want to use modelsim but you are talking about quartus. Just compile and simulate in modelsim directly.
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--- Quote Start --- I know that real data type can not be synthesized on FPGA. I just want to check my result on ModelSim. Therefore, I just use "Analysis and Elaboration" option for compilation of my project. --- Quote End --- therefore, you'll use real type only in test benches. Or exclude the respective code from synthesis by synthesis off attributes.

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