Convert FIR compiler and FTT into SOPC ready IPs using SOPC component editor

[Altera_Forum]

Hi, all, 

 I am trying to convert the FIR compiler and FTT, which are all DSP builder ready components into SOPC ready components using the component editor.  Up till now, I have read documents about component editor but still I am not very clear on how to start this, or is it possible at all?  Can any one suggest on how to start? e.g. what information I need to sort out first? read the user guide of FIR compiler first or something else?  I appreciate your advice!

[Altera_Forum]

btw, sorry that i forgot to mention, ultimately I would like to use SOPC to interface these two components and also let them run in different clock domains... possible to do that? thx!!

[Altera_Forum]

I've not used the FIR & FFT cores directly. However, I glanced at the list of signals and it seems to me you shouldn't have any trouble doing what your want. Here is what I would do. 

 1 - Read the Avalon Interface Specification: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 2 - Generate your FFT and FIR cores as you would normally. 3 - For each core, I would create a wrapper HDL file (this will become your SoPC builder component). In this wrapper HDL file, I would connect up any ports to the IP core that need to be connected to the outside world. Also, if you are going to create some logic that bridges between the Avalon MM world and the IP core, this is the place to do it. For example, I see the FFT core has a few ports (fftpts_in, fftpts_out, inverse, etc.). These won't connect directly to the Avalon bus (though you can export them out of the SoPC system if you want). So you may want to create some addressable registers in your wrapper file to drive these signals. 4 - Create a component using the component wizard.  http://www.altera.com/literature/hb/qts/qts_qii54005.pdf http://www.altera.com/literature/hb/qts/qts_qii54007.pdf  Your HDL wrapper will be the top-level file for the component. Your component will need: a - One avalon streaming sink b - One avalon streaming source c - Optionally an avalon MM slave interface. d - Optionally a conduit interface if you are going to export any of the signals directly out of SoPC builder.  Jake

[Altera_Forum]

--- Quote Start ---  I've not used the FIR & FFT cores directly. However, I glanced at the list of signals and it seems to me you shouldn't have any trouble doing what your want. Here is what I would do.  1 - Read the Avalon Interface Specification: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 2 - Generate your FFT and FIR cores as you would normally. 3 - For each core, I would create a wrapper HDL file (this will become your SoPC builder component). In this wrapper HDL file, I would connect up any ports to the IP core that need to be connected to the outside world. Also, if you are going to create some logic that bridges between the Avalon MM world and the IP core, this is the place to do it. For example, I see the FFT core has a few ports (fftpts_in, fftpts_out, inverse, etc.). These won't connect directly to the Avalon bus (though you can export them out of the SoPC system if you want). So you may want to create some addressable registers in your wrapper file to drive these signals. 4 - Create a component using the component wizard.  http://www.altera.com/literature/hb/qts/qts_qii54005.pdf http://www.altera.com/literature/hb/qts/qts_qii54007.pdf  Your HDL wrapper will be the top-level file for the component. Your component will need: a - One avalon streaming sink b - One avalon streaming source c - Optionally an avalon MM slave interface. d - Optionally a conduit interface if you are going to export any of the signals directly out of SoPC builder.  Jake  --- Quote End ---    Dear Jake,  I appreciate for your thorough plan!   I am now going to try out on my own according to your suggestion. It helps me a lot to get the ideas into shape. I may post questions again in this thread if any one comes up in the future~~  Best regards

[Altera_Forum]

Hi, I am now using the component editor to create FFT component for SOPC Builder. My system only contains FFT and FIR, and FFT is supposed to be the slave of FIR. Here are some of my doubts: 

 First, for the signal named "clk", should its interface be "clock_reset" or "clock input " or "clock output" or anything else?   Second, there is a signal called "inverse", seems it doesn't belong to the Avalon ST interface signals, why does it appear in the component editor? How should I define its interface as well as signal type?   Third, if I were not to connect any component to FFT; hence, in order to obtain its output data, Must I set its output signal (source_real, source_img) to be conduit interface type?   Thanks a lot for your kind advice!

[Altera_Forum]

Hi, everyone, I have summarized all of my problems in another post at http://www.alteraforum.com/forum/showthread.php?t=20256 

 Please kindly help me in that post. Thanks you so much and my apology for any inconvenience caused.