Convert Verilog Input file to VHDL

[Altera_Forum]

I inherited a Verilog HDL from a friend. However I do not know Verilog. I want to convert the file to VHDL format to edit the file. I opened the Verilog file, and I see the Create/Update button. However the first line item to convert to HDL file is unhighlighted. I am not sure what is the issue. Can someone help me figure out the issue? 

Unfortunately the file is too big to attache. I hope someone else has seen the problem and can help without the real *.v file.

[Altera_Forum]

Quartus does not convert Verilog to VHDL. I believe it's only for schematic files. (Their used to be some tools out there for this, but the free ones never worked that well, i.e. you usually had to modify it some yourself). If it's pretty simple HDL, they may be fine, although if you know VHDL well it will not be hard to read. If it's complicated Verilog that uses the more abstract parts of the language, the tools may not work that well anyway. It's not like there is a clear 1:1 translation between all constructs, so if it gets complicated you probably don't want a tool converting it anyway.

[Altera_Forum]

You can try x-hdl (http://www.x-tekcorp.com/xhdl.html) - with which I've had modest success in the past. However, it's not a polished product and, as Rysc suggested, doesn't convert some constructs correctly. 

 I'd suggest that, depending on your VHDL fluency, you should be able to understand the verilog constructs. There is also plenty of online help and basic tutorials that will help. Try this verilog tutorial (http://www.asic-world.com/verilog/veritut.html) site.  Cheers, Alex