Copying input signal to output through I/O buffers on Cyclone III

Altera_Forum · ‎06-21-2014

Hello Altera Forum community,

I am an FPGA beginner trying to design a Cyclone III so that it outputs replica signals of a common input signal (also planning to implement a counter and a strobe signals generator on the same chip).

As the simplest case of 1-input/1-output, I have written the following Verilog HDL code:


module iobuftest1(
            clk_in,
            clk_out
           );
input clk_in;
output clk_out;
assign clk_out = clk_in;
endmodule

After full compilation, Quartus II replaces the assign statement (assign clk_out = clk_in;) by the following code in the .vo output file:


wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("iobuftest1_v.sdo");
// synopsys translate_on
wire \clk_out~output_o ;
wire \clk_in~input_o ;
// Location: IOOBUF_X11_Y29_N2
cycloneiii_io_obuf \clk_out~output (
    .i(\clk_in~input_o ),
    .oe(vcc),
    .seriesterminationcontrol(16'b0000000000000000),
    .devoe(devoe),
    .o(\clk_out~output_o ),
    .obar());
// synopsys translate_off
defparam \clk_out~output .bus_hold = "false";
defparam \clk_out~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X14_Y29_N22
cycloneiii_io_ibuf \clk_in~input (
    .i(clk_in),
    .ibar(gnd),
    .o(\clk_in~input_o ));
// synopsys translate_off
defparam \clk_in~input .bus_hold = "false";
defparam \clk_in~input .simulate_z_as = "z";
// synopsys translate_on
assign clk_out = \clk_out~output_o ;

I have confirmed that an input buffer ("cycloneiii_io_ibuf") and an output buffer ("cyloneiii_io_obuf") are inserted between the input and output nodes in the Technology Map Viewer and the Resource Property Editor.

I am OK with this insertion from the viewpoint of output driving capability.

The problem, however, is that the input signal "clk_in" is not copied to the output signal "clk_out" in simulation results by ModelSim-Altera.

After several clock periods of "X", "clk_out" abruptly goes to "0" and remains so throughout the simulation.

Could you tell me how to make "clk_out" an exact replica of "clk_in", possibly keeping the I/O buffers?

Thanks in advance.

kima

Altera_Forum · ‎06-24-2014

I have found in the testbench that the clock period of the input "clk_in" (1ns) was shorter than the delay between the input and output (~7ns).

Much slower "clk_in" has allowed "clk_out" to follow the transition.

Thanks for taking time.

kima