NIOSII Boot Configuration with EPCS and JTAG-SFL

[Altera_Forum]

Hello, 

 i have a problem with configuring and booting my system from an epcs device. The topic is more about the correct design-flow, so i think this should be the right sub-fourm.  the test-system The hardware i am experimenting on is a DE0 board from Terasic. It has a EP3C16 FPGA with an EPCS16 Flash connected. I generated an QSYS design with Clock Source, NiosIIe, On-Chip RAM, RS232 UART, System ID, Timer, JTAG UART, Parallel I/O, and EPCS Serial Flash Controller. The reset vector is set to the EPCS controller, the exception vector is set to the ram. The software consists of a RS232 console that controls on-board LEDs with the parallel I/O.  what does work I can configure the FPGA via JTAG or via AS (after programming the EPCS device via JTAG SFL), both works well. This means only FPGA configuration, no software loading. In Eclipse i can download the software via JTAG and run it. Principally all works.  what does not work The next step i want to learn is how to load software from the epcs device. I am still working for some days and it does not work.  workflow I build the software in eclipse and use "make mem_init_generate" to build a hex-file from the elf-file. In Quartus i try to read the hex-file within the "Convert Programming File" - dialog. The generation of the JTAG Indirect Configuration File fails with the message "Data in HEX File overlaps between data blocks at address 8 and address 0".  Here i found a description of a nearly similar problem: .altera.com/support/kdb/solutions/rd09282011_907.html But the solution does not work, maybe because its Quatrus 11.0 and i am using 12.0.  my question Can anyone tell me a workflow for programming FPGA configuration data and software into a EPCS device via JTAG SFL?  best regards, lodentoni

[Altera_Forum]

You shouldn't generate an .hex file from your application. This is only used when the CPU can directly access the program memory, so for example when using a parallel flash or an on-chip memory. When using the EPCS you need a "pre-digested" version of the .elf file, written on the EPCS just after the .sof image. The elf2flash commang line tool can convert a .elf to an .srec ready to be written to the EPCS using nios2-flash-programmer. IIRC the graphical version of the Nios II flash programmer can also do both steps directly from Eclipse.

[Altera_Forum]

--- Quote Start ---  The elf2flash commang line tool can convert a .elf to an .srec ready to be written to the EPCS using nios2-flash-programmer. IIRC the graphical version of the Nios II flash programmer can also do both steps directly from Eclipse.   --- Quote End ---   I am not shure what the IIRC is. In eclipse i can right-klick on a software project and select "Nios II" -> "Flash Programmer ...". I think this is the tool you mean and i tried it. In the tool i added the .sof and .elf files to the "Files for flash conversion" - List and started the process without success. Ths is the output:   Info: 16.04.2013 16:10:54 - (FEIN) sof2flash: Starting Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.opt Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/NIOS_SYSTEM.sof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Tue Apr 16 16:11:01 2013 Info: Info: Elapsed time: 00:00:07 Info: Info: Total CPU time (on all processors): 00:00:02 Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.rpd Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Tue Apr 16 16:11:11 2013 Info: Info: Elapsed time: 00:00:10 Info: Info: Total CPU time (on all processors): 00:00:02 Info: 16.04.2013 16:11:13 - (FEIN) sof2flash: Done Info: Using cable "USB-Blaster ", device 1, instance 0x00 Info: Resetting and pausing target processor: OK Info: Reading System ID at address 0x00022080: Info: ID value does not match: read 0x0000000D; expected 0x00000013 Info: Timestamp value was not verified: value was not specified Info: Warning: The software you are downloading may not run on the system which Info: is currently configured into the device. Info: Processor data bus width is 32 bits Info: Looking for EPCS registers at address 0x00021800 (with 32bit alignment) Info: Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021900 (with 32bit alignment) Info: Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021A00 (with 32bit alignment) Info: Initial values: 108001C4 1004D0FA 002EE03A 003F9C06 002EE03A 003F9506 Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021B00 (with 32bit alignment) Info: Initial values: 00000000 00000000 00000000 00000000 00000000 00000000 Info: Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16) Info: Looking for EPCS registers at address 0x00021C00 (with 32bit alignment) Info: Initial values: 00000000 00000000 00000260 00000000 00000000 00000001 Info: Valid registers found Info: EPCS signature is 0x00 Info: EPCS identifier is 0x000000 Info: No EPCS layout data - looking for section Info: Unable to use EPCS device Info: Leaving target processor paused Error: Error code: 8 for command: $SOPC_KIT_NIOS2/bin/nios2-flash-programmer "Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.flash" --base=0x21800 --epcs --sidp=0x22080 --id=0x13 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on localhost ' --program --verbose   The problem seems to be that an EPCS128 is used as target while an EPCS16 exist in the real hardware. (The tool reads 0x0 as EPCS identifier, this looks like there is another problem.) I don't found an option to change the target device. Do you know where the flash programmer gets the information?

[Altera_Forum]

Hi lodentoni, 

 You can change the target cofiguration device in Quartus, Assignments->Device->Device and Pin Options->configuration->configuration device ... (needs recompilation).  Best Regards, laland

[Altera_Forum]

The --device=EPCS128 isn't actually relevant, I've seen it used on all EPCS devices. I think Altera should just rename it to --device=EPCS ;) 

Looking at your log I see a more interesting error:Info: Reading System ID at address 0x00022080: Info: ID value does not match: read 0x0000000D; expected 0x00000013 Info: Timestamp value was not verified: value was not specifiedThis indicates that the image currently in the FPGA isn't what the programmer expects. As it is still trying to flash the EPCS anyway, it probably means that you disabled the system ID check in Eclipse. This isn't recommended. If the the system ID check is enabled, when you have a system ID error then you will just get an error message and the flash programmer will stop, which is better. So now you need to figure out why you don't have the expected image. You need to be sure that the .sof image currently in your FPGA corresponds to the .sopcinfo file that was used to generate the BSP. Each time you do a change in the QSYS/SOPC builder system, after regeneration you need to recompile the Quartus project and regenerate the BSP. Then upload the new .sof file to the FPGA and you can use the Nios flash programmer.

[Altera_Forum]

--- Quote Start ---  Hi lodentoni,  You can change the target cofiguration device in Quartus, Assignments->Device->Device and Pin Options->configuration->configuration device ... (needs recompilation).  Best Regards, laland  --- Quote End ---     --- Quote Start ---  The --device=EPCS128 isn't actually relevant, I've seen it used on all EPCS devices. I think Altera should just rename it to --device=EPCS ;)  --- Quote End ---   Hi Laland, i tried this but it still shows the EPCS128 as device.     --- Quote Start ---  Looking at your log I see a more interesting error:Info: Reading System ID at address 0x00022080: Info: ID value does not match: read 0x0000000D; expected 0x00000013 Info: Timestamp value was not verified: value was not specifiedThis indicates that the image currently in the FPGA isn't what the programmer expects. As it is still trying to flash the EPCS anyway, it probably means that you disabled the system ID check in Eclipse. This isn't recommended. If the the system ID check is enabled, when you have a system ID error then you will just get an error message and the flash programmer will stop, which is better. So now you need to figure out why you don't have the expected image. You need to be sure that the .sof image currently in your FPGA corresponds to the .sopcinfo file that was used to generate the BSP. Each time you do a change in the QSYS/SOPC builder system, after regeneration you need to recompile the Quartus project and regenerate the BSP. Then upload the new .sof file to the FPGA and you can use the Nios flash programmer.  --- Quote End ---    Now i am a little bit confused. I thought the flash programmer brings the fpga configuration and the software image into the epcs device. I disabled the SystemID check because i know that the fpga was not configured. Do you mean i have to configure the fpga with quartus device programmer and than use the flash programmer to to write fpga configuration and software data into the epcs? I tried this and it does not work.  The next thing i tryed is to use the quartus device programmer to write the fpga configuration into the epcs device (without software image). Then i reset the fpga and try to use the flash programmer. This time it detects the correct SystemID (because the fpga is configured) but it seems that a problem exist on detecting the epcs device:  Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.opt Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/NIOS_SYSTEM.sof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Thu Apr 18 10:31:27 2013 Info: Info: Elapsed time: 00:00:06 Info: Info: Total CPU time (on all processors): 00:00:02 Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.rpd Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Thu Apr 18 10:31:38 2013 Info: Info: Elapsed time: 00:00:10 Info: Info: Total CPU time (on all processors): 00:00:02 Info: Using cable "USB-Blaster ", device 1, instance 0x00 Info: Resetting and pausing target processor: OK Info: Reading System ID at address 0x00022080: verified Info: No EPCS layout data - looking for section Info: Unable to use EPCS device Info: Leaving target processor paused Error: Error code: 8 for command: $SOPC_KIT_NIOS2/bin/nios2-flash-programmer "Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.flash" --base=0x21800 --epcs --sidp=0x22080 --id=0x16 --timestamp=1366205590 --device=1 --instance=0 '--cable=USB-Blaster on localhost ' --program

[Altera_Forum]

Hi lodentoni, 

 As Daixiwen told --device=EPCS128 isn't actually relevant. I checked my design and it's the same. So forget about the EPCS128.  I am also trying to program my board with FPGA configuration and NIOS s/w, but not able to succeed. You need to program the FPGA with *.sof, reset the board so that FPGA is configured before you use the Flash programmer from NIOS IDE.  If EPCS device is not getting detected even after programming FPGA, then you need to check whether the EPCS flash controller pins are exported to top level or not in FPGA design.  I tried flash programming indirectly without using NIOS IDE and itseems to be working at the moment. (used the commands from http://www.alteraforum.com/forum/showthread.php?t=31375&p=127299#post127299).  Best Regards, Laland

[Altera_Forum]

You basically have 3 ways to program an EPCS chip:[list][*]connect the EPCS directly to the USB blaster. This requires an additional connector on your board, different from the JTAG one[*]Generate a .jic file containing everything you need and use the Quartus programmer to program the EPCS through JTAG. The programmer will upload an SFL image to the FPGA, and this SFL image will connect the EPCS pins to a virtual JTAG component that the Quartus programmer can then access to programm the EPCS[*]Use the Nios II Flash programmer. This programmer also uses JTAG, but instead of an SFL image, needs an FPGA image with a Nios II CPU. Then it will use the JTAG module inside the Nios CPU to access the EPCS controller component inside the FPGA, and that way access the EPCS.[/list]You are currently using method 3, and that is why it requires an FPGA image with a Nios CPU and an EPCS controller. It also needs the *right* FPGA image to be there, because it needs to know what address to use to access the EPCS controller. 

As for your current error, I agree with laland. It looks like it nos finds the EPCS controller, but somehow doesn't manage to communicate with the EPCS chip itself. Check that the EPCS controller ports are connected to the right FPGA pins, and if possible check with a scope the signals between the FPGA and the EPCS chip to see if anything is happening there when you try to program the flash.

[Altera_Forum]

Hi lodentoni, 

 As Daixiwen told --device=EPCS128 isn't actually relevant. I checked my design and it's the same. So forget about the EPCS128.  I am also trying to program my board with FPGA configuartion and NIOS s/w, but not able to succeed. You need to program the FPGA with *.sof, reset the board so that FPGA is configured before you use the Flash programmer from NIOS IDE.  If EPCS device is not getting detected even after programming FPGA, then you need to check whether the EPCS flash controller pins are exported to top level or not in FPGA design.  I tried flash programming indirecly without using NIOS IDE and itseems to be working at the moment. (use the command line http://www.alteraforum.com/forum/showthread.php?t=31375&p=127299#post127299).  Best Regards, Laland  PS: Posted this yesterday, but ot ale to ind on thread. So reposting.

[Altera_Forum]

--- Quote Start ---  [list][*]Generate a .jic file containing everything you need and use the Quartus programmer to program the EPCS through JTAG. The programmer will upload an SFL image to the FPGA, and this SFL image will connect the EPCS pins to a virtual JTAG component that the Quartus programmer can then access to programm the EPCS[/list]  --- Quote End ---   This was my preferred solution. But as described in my earlier posts, no of the workflows i read and try were successful. It fail to generate the jic file with fpga configuration and software image.    --- Quote Start ---  [list][*]Use the Nios II Flash programmer. This programmer also uses JTAG, but instead of an SFL image, needs an FPGA image with a Nios II CPU. Then it will use the JTAG module inside the Nios CPU to access the EPCS controller component inside the FPGA, and that way access the EPCS.[/list]  --- Quote End ---   This is complete new to me. I thought the flash programmer uses also a kind of SFL design to write to the epcs flash. Anyway, i tried to configure the fpga via jtag and then to use the flash programmer, wich was not successful.    --- Quote Start ---  It looks like it nos finds the EPCS controller, but somehow doesn't manage to communicate with the EPCS chip itself. Check that the EPCS controller ports are connected to the right FPGA pins, and if possible check with a scope the signals between the FPGA and the EPCS chip to see if anything is happening there when you try to program the flash.  --- Quote End ---   I checked the clock signlas of the epcs device. There is no activity while using the flash programmer. In the Embedded Peripherals IP User Guide i read, the connections for the EPCS Controller where automatically generated. But there are some exceptions to Cyclone III devices. So i try to uncheck the automatic detection of connections in the EPCS Controller MegaWizard and place the connections manually. But then the fitter brings an error message because of placing two signals to one pin (the manually placed epcs controller signals and automatically generated signals "~ALTERA_*").  Do anyone know how how the EPCS Controller is correctly implemented in Cyclone III designs? In the Embedded Peripherals IP Guide is written that something is to respect with cyclone III devices but i can't find a manual in which is written what exactly is to do.

[Altera_Forum]

Hi lodentoni, 

 I am also in the same situation, but I am able to program the EPCS16 device with sof + elf file. I am not able to use the flash programmer as the program always fails to reset (after it earases and writes EPCS16). Hence I know EPCS is detected atleast.  But I tried a different appoach of converting the sof and elf files to *.flash, again to *.bin, combine both and then covert to *.hex. Now use the Quartus programmer to convert the file to jic file to program EPCS16. This is a long process but it worked for me. Used NIOS command line for file conversion.  Regarding the EPCS1 device not detected, as far as I know CycloneIII and IV requires the signals from the IP to be ported to top level. Then maually assign DCLK, SDO... pins using assignment editor. Also you need to make these pins as user IO's in Device settings (Dual purpose pins, set as reular I/Os). See ug_embedded_ip, page 53.  The normal JTAG option works if you don't do this also, so we tend to think EPCS connections are fine.  Best Regards, laland

[Altera_Forum]

Yes, setting the pins as regular I/O should solve your problems. 

 As for the .jic workflow with an .elf file, AFAIK the only tool that can generate a correct bitstream for an EPCS chip from the .elf file is the command line tool elf2flash (the one called automatically from the Nios Flash Programmer). Unfortunately this tools generates a .srec file, which the Nios flash programmer is quite happy with, but that the Quartus programmer doesn't understand. (why, Altera, why do you make our lives so complicated???). So you need to convert this .srec file to the .hex format to make the Quartus programmer happy. A tool such as srec_cat (http://srecord.sourceforge.net/) can do that directly, or you can do as laland suggests and convert it to a binary format first and then to .hex If you are using graphical tools from Eclipse I think the easiest workflow is the Nios flash programmer.

[Altera_Forum]

--- Quote Start ---  Also you need to make these pins as user IO's in Device settings (Dual purpose pins, set as reular I/Os). See ug_embedded_ip, page 53.  --- Quote End ---   Ok thanks, i overlooked this point. Now i can set the epcs signals manually. I did it and recompile the fpga design, regenerate the bsp and rebuild the software. When i start the flash programmer it is still not successfull and the epcs clock line still shows no activity.    --- Quote Start ---  Yes, setting the pins as regular I/O should solve your problems.  --- Quote End ---   Unfortunately it does not.    --- Quote Start ---  But I tried a different appoach of converting the sof and elf files to *.flash, again to *.bin, combine both and then covert to *.hex. Now use the Quartus programmer to convert the file to jic file to program EPCS16. This is a long process but it worked for me. Used NIOS command line for file conversion.  --- Quote End ---   What exactly is the bin file format and how is it created from a flash format? There is a tool flash2dat, but no tools like dat2hex or bin2hex? What do you use to convert these formats. I also found a tool elf2hex. But i am confused about settin as start- and end-adresses. Do I neet to set the ram adresses, the epcs controller adresses, or anything else?    --- Quote Start ---  A tool such as srec_cat (http://srecord.sourceforge.net/) can do that directly, ...  --- Quote End ---   Here i'm working under windows. For development tasks i still installed cygwin. SRecord is not in the cygwin package repositorys. A first "./configure" shows that installing it manully is a complete new challenge.

[Altera_Forum]

Are you sure that the EPCS is working properly? You can use the Quartus programmer, upload an SFL image (you should find as ready compiled one as C:\altera\xx.x\quartus\common\devinfo\programmer\sfl_fpga_name.sof) and then do a new autodetect. Then it should show you the EPCS connected to the FPGA. Using a scope you should see the EPCS lines toggling and use it as a reference. Once you have that working you know that the communication between the EPCS and the FPGA is working properly and can focus on the Nios II flash programmer. 

The only two explanations I can think of for your problem would be wrong pin assignment (chip select instead of clock, for example) or wrong EPCS controller address. As long as you are sure that the image in the FPGA matches the .sopcinfo file that the Nios Flash programmer uses (which it should, now that you have enabled the system ID check) you should have the correct EPCS controller address so I don't understant why the EPCS lines aren't even toggling.  As for SRecord, it looks like the author is rather stubborn about a Windows version... He doesn't even want to host a ready compiled version made by someone else... But there is a page explaining how to compile it, it looks like there are two dependencies to install: boost and libgcrypt: http://srecord.sourceforge.net/windows.html  You can't use elf2hex because it is only meant to be used for parallel memories directly connected to the CPU's masters. For the EPCS your first mandatory step is elf2flash, to convert your .elf application to a format understood by the EPCS bootloader. But except elf2flash I don't use Altera's flash conversion utilities any more. I find SRecord a lot more versatile, and it has cool features such as automatic checksum generation.

[Altera_Forum]

--- Quote Start ---  Are you sure that the EPCS is working properly?  --- Quote End ---   Yes, before using NIOSII i set up a simple fpga configuration which flashes some LEDs. I wrote the design to the EPCS device and repower the fpga. The design was loaded from the epcs and the LEDs where flashing.    --- Quote Start ---  You can use the Quartus programmer, upload an SFL image (you should find as ready compiled one as C:\altera\xx.x\quartus\common\devinfo\programmer\sfl_fpga_name.sof) and then do a new autodetect. Then it should show you the EPCS connected to the FPGA. Using a scope you should see the EPCS lines toggling and use it as a reference.  --- Quote End ---   Ok I've done this and it works. The EPCS16 device was detected properly and the epcs clock line has activity.    --- Quote Start ---  Once you have that working you know that the communication between the EPCS and the FPGA is working properly and can focus on the Nios II flash programmer. The only two explanations I can think of for your problem would be wrong pin assignment (chip select instead of clock, for example)  --- Quote End ---   I checked the pin assignement against the schematic of the board and against "Pin Information for the Cyclone ® III EP3C16 Device Version 1.3". It seems to be Okay.  

• dclk -> K2 (DCLK) 
• sdo -> D1 (DATA1, ASDO) 
• data0 -> K1 (DATA0) 
• sce -> E2 (FLASH_nCE, nCSO) 

     --- Quote Start ---  [...] or wrong EPCS controller address. As long as you are sure that the image in the FPGA matches the .sopcinfo file that the Nios Flash programmer uses (which it should, now that you have enabled the system ID check) you should have the correct EPCS controller address so I don't understant why the EPCS lines aren't even toggling.  --- Quote End ---   In Qsys the mapping of the epcs controller is 0x21800-0x21fff. This seems to be the same for the flash-programmer.  Maybe i use the flash-rpgrammer incorrect. Here is my workflow: [list] [*]at first i use the quartus programmer to erase the EPCS device [*]now i load the fpga configuration (*.sof file) with the quartus programmer via jtag into the fpga [*]i choose "Run As -> NIOSII Hardware" from the Eclipse project menu [*]now the system is running in the fpga (not written in the epcs -> volatile) [*]i click "Terminate and Remove Launch" in the NIOSII console window to release the USB Blaster [*]i choose "NIOS II -> Flash Programmer" from the Eclipse project menu [*]after selecting "File -> New" i select hte *.sopcinfo file [*]i add the *.sof file [*]i add the *.elf file [*]i cklick start [/list]  There was no activity at the clock lines. I noticed, that the system on the fpga was stopped. This is the output of the flash programmer:  Info: 23.04.2013 15:04:07 - (FEIN) sof2flash: Starting Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.opt Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/NIOS_SYSTEM.sof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Tue Apr 23 15:04:16 2013 Info: Info: Elapsed time: 00:00:09 Info: Info: Total CPU time (on all processors): 00:00:02 Info: Info: ******************************************************************* Info: Info: Running Quartus II 32-bit Convert_programming_file Info: Info: Command: quartus_cpf --no_banner --convert Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.rpd Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings Info: Info: Peak virtual memory: 126 megabytes Info: Info: Processing ended: Tue Apr 23 15:04:31 2013 Info: Info: Elapsed time: 00:00:15 Info: Info: Total CPU time (on all processors): 00:00:02 Info: 23.04.2013 15:04:33 - (FEIN) sof2flash: Done Info: Using cable "USB-Blaster ", device 1, instance 0x00 Info: Resetting and pausing target processor: OK Info: Reading System ID at address 0x00022080: verified Info: Processor data bus width is 32 bits Info: Looking for EPCS registers at address 0x00021800 (with 32bit alignment) Info: Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021900 (with 32bit alignment) Info: Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021A00 (with 32bit alignment) Info: Initial values: 108001C4 1004D0FA 002EE03A 003F9C06 002EE03A 003F9506 Info: Not here: reserved fields are non-zero Info: Looking for EPCS registers at address 0x00021B00 (with 32bit alignment) Info: Initial values: 00000000 00000000 00000000 00000000 00000000 00000000 Info: Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16) Info: Looking for EPCS registers at address 0x00021C00 (with 32bit alignment) Info: Initial values: 00000014 00000014 00000260 00000000 00000014 00000001 Info: Not here: reserved fields are non-zero Info: No EPCS registers found: tried looking at addresses Info: 0x00021800, 0x00021900, 0x00021A00, 0x00021B00 and 0x00021C00 Info: Leaving target processor paused Error: Error code: 8 for command: $SOPC_KIT_NIOS2/bin/nios2-flash-programmer "Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.flash" --base=0x21800 --epcs --sidp=0x22080 --id=0x16 --timestamp=1366718316 --device=1 --instance=0 '--cable=USB-Blaster on localhost ' --program --verbose

[Altera_Forum]

Hi  

 Commands to generate the hex file are given below.  sof2flash --epcs --compress --input=VHDL.sof --output=firmware.flash  elf2flash --epcs --after=firmware.flash --input=nios.elf --output=software.flash  nios2-elf-objcopy -I srec -O binary firmware.flash firmware.bin nios2-elf-objcopy -I srec -O binary software.flash software.bin  cat firmware.bin software.bin > app_image.bin  nios2-elf-objcopy -I binary -O ihex app_image.bin app_image.hex  UsecQuartus pogrammer to convert this hex file to jic and program the board.  Using the above procedure, I am able to program the board and FPGA configures properly.

[Altera_Forum]

--- Quote Start ---  elf2flash --epcs --after=firmware.flash --input=nios.elf --output=software.flash  --- Quote End ---    Hi laland. This program wants base adress and end adress specified. I can't find out what adresses are meant. Trying the ram and the epcs controller adress space does not work. I wonder what adresses are meant.  The help of elf2flash says this are the adresses of the flash. But the epcs flash device is not mapped directly to the processor. The epcs controller is mapped from 0x21820 to 0x21fff. This is a adress space ok about 1,9kiB. My EPCS16 has 16Mbit ~ 1,9MiB of space.    --- Quote Start ---  Daixiwen: Are you sure that the EPCS is working properly?  --- Quote End ---   Meanwhile i wrote a little program that writes "hello world" to a space in the EPC device by using the HAL driver of the epcs controller. After repowering the fpga and configure it again i can read the hello world string from the EPCS device. At reading and writing i can trigger activitiy at the clock signal of the epcs device. So the connection / pin planning and the proper function of the epcs device is approved. (Using the flash programmer does still not work).

[Altera_Forum]

Hi,  

I used this command as it is, without specifying the start and end address of EPCS16.  I picked up those commands from another thread here on this forum. Do you get error when you execute that command?  You are right that EPCS address is not directly mapped to processor.So end address is not known.

[Altera_Forum]

Okay, my fault. There was a typo on the command line. I can generate the hex file and write it into the EPCS device. Thank you for your suggestions. 

 After repowering the fpga nothing happens, the system does not start. If i reset the nios2 processor (with a button on the board) I can see activity on the epcs clock line. It seems that the nios2 loads the software after a reset. But the software does not run.  Only if I open the nios2-terminal, to have a look at the JTAG UART module, the system starts. Is there a hidden handbrake anywhere which i have to respect?

[Altera_Forum]

Yes the elf2flash shouldn't ask for start or end addresses when you are using the --epcs and --after options, it will automatically put the data after the FPGA image. 

 Which embedded OS are you using, if any? Are you using the reduced drivers or the full ones? I know that some versions of the JTAG UART driver will block any writing transaction until a USB blaster is connected (it is the case with the eCos driver, for example, but IIRC the full version from the Altera HAL or with uC OS doesn't have this problem). If in doubt you can have a look at the driver source code, it isn't that complicated.  As for your problem with the Nios flash programmer, I'm out of ideas. It looks like it doesn't find the SPI master at the expected address. It should fail on the first set of addresses, but should find it 1kbyte after the base address. As an example, here is a read operation done on a board with a Cyclone III and an EPCS64:$ nios2-flash-programmer -c 3 -b 0x03400800 --epcs -R dump.flash --debug Using cable "USB-Blaster on 192.168.0.74 ", device 1, instance 0x00 Resetting and pausing target processor: OK Processor data bus width is 32 bits Looking for EPCS registers at address 0x03400800 (with 32bit alignment) Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A Not here: reserved fields are non-zero Looking for EPCS registers at address 0x03400900 (with 32bit alignment) Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C Not here: reserved fields are non-zero Looking for EPCS registers at address 0x03400A00 (with 32bit alignment) Initial values: 108001C4 1004D0FA 002EE03A 003F9C06 002EE03A 003F9506 Not here: reserved fields are non-zero Looking for EPCS registers at address 0x03400B00 (with 32bit alignment) Initial values: 00000000 00000000 00000000 00000000 00000000 00000000 Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16) Looking for EPCS registers at address 0x03400C00 (with 32bit alignment) Initial values: 00000000 00000000 00000260 00000000 00000000 00000001 Valid registers found EPCS signature is 0x16 EPCS identifier is 0x202017 Using EPCS size information from section Device size is 8MByte (64Mbit) Erase regions are: offset 0: 128 x 64K EPCS status is 0x00 Read 8192KB in 70.8s (115.7KB/s) Writing EPCS contents to dump.flash Leaving target processor pausedYour workflow seems correct to. You could try and run the flash programmer right after you put the .sof flash, without running the embedded software first. Maybe the embedded software screws up the EPCS controller...

[Altera_Forum]

--- Quote Start ---  Which embedded OS are you using, if any? Are you using the reduced drivers or the full ones? I know that some versions of the JTAG UART driver will block any writing transaction until a USB blaster is connected (it is the case with the eCos driver, for example, but IIRC the full version from the Altera HAL or with uC OS doesn't have this problem).  --- Quote End ---   Until now I don't use any OS, only the HAL. Deactivating the UART-JTAG driver solves the problem, now the system starts up after reset (without nios2-terminal).    --- Quote Start ---  As for your problem with the Nios flash programmer, I'm out of ideas. It looks like it doesn't find the SPI master at the expected address. It should fail on the first set of addresses, but should find it 1kbyte after the base address. As an example, here is a read operation done on a board with a Cyclone III and an EPCS64: [...] Your workflow seems correct to. You could try and run the flash programmer right after you put the .sof flash, without running the embedded software first. Maybe the embedded software screws up the EPCS controller...  --- Quote End ---    The reading of the EPCS registers somtimes fails at the first register and sometimes at a higher register. Running the flash programmer right after putting the sof file to the fpga does also not work. I don't waste any more time with the flash programmer and use the workflow described by laland. In any case, using command line tools is more favour to me. I will try to do my builds etc. per command line. Eclipse is uncomfortable slow, but for the first steps it was useful.  I think my Problem is solved and i can program my software to a epcs device. Much thanks to Daixiwn and laland, you helped me alot!  best regards, lodentoni