It appears that Verilog preprocessor in Quartus is not quite standard-conformant, the usual string concatenation trick does not work.
For example, the following will fail:
`define PREFIX . `define IPATH(a) `include `STR(`PREFIX/a) `IPATH(include.v)
Quartus II Lite, 18.1, but it's the same with the previous versions as well. Fails with "missing compiler directive" error, detailed logs show that the macro expansion order is wrong (and it's a very common bug for quite a few Verilog preprocessors in the industry).
Sorry, I forgot to include STR definition. Assume you have a file 'defines.v', can be empty, does not matter, and a file 'main.v' with the following:
`define STR(a) `"a`" `define PREFIX . `define IPATH(a) `include `STR(`PREFIX/a) `IPATH(defines.v)
Then, Quartus II will display two errors for the line 5:
Error (10108): Verilog HDL Compiler Directive error at main.v(5): missing Compiler Directive Error (10096): Verilog HDL Compiler Directive error at main.v(5): incorrect use of predefined text macro "include" -- expected macro field ""filename""
It took me some time to figure out the root cause of this error. Thanks for your patience and understanding.
I tried to test the definition in another edition of the Intel Quartus Prime software, pro edition. The compilation was successful. I believe that this error is due to the limitation of the Standard edition software in SystemVerilog language support.
You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pd... for software comparison.
Hi KYeoh, thanks for your answer!
I was under impression (from the detailed error messages), that the `" directive worked as expected, and it was the expansion order that was incorrect. Maybe I'm wrong, I'll try to construct more tests to check this.
As for the expansion order, it's specified in IEEE 1364-2001, par. 19.3.1.