Creating A Modular Design

[Altera_Forum]

I was wondering if there was a way to automatically begin the name of a megafunction with specific text. 

 For example, lets say I have two blocks in my design we'll call FIR_8D and BUS_CTRL. Each of these blocks contains it's own logic/megafunctions/VHDL specific to it's operation. I'd like to reuse the block called FIR_8D in multiple designs.  What I've been doing is whenever I create a new megafunction or VHDL file, I've been appending to the beginning of the file name. For example if I created a mux that has 2 inputs and 16bits each, I would create the megafunction with the name "FIR_8D_mux2x16". This way I know that the mux belongs to the FIR_8D block.  Is there an easier/automatic way to always append to the beginning of a file name like this?  Currently I'm using Quartus II version 9.1. Even if this version doesn't have the capability to do this, is there a newer version that does?  Thank you!

[Altera_Forum]

In Vhdl there are not these problems....you can try to create a project_top.vhdl in which you istanziate other sub-modules....mux,decoder,registers...for your custom design....every module can be istanziated many times...even if it has the same name declared in its sub_module.vhdl file 

For example...  Project-top.vhdl  Reg.vhdl  Dec.vhdl  Mux.vhdl  In Project-top.vhdl you can istanziate Reg.vhdl, for example, there Times  Component Reg Port(); End component;  Component Dec Port(); End component;  Component Mux Port(); End component;    Inst1: Reg Port map(); Inst2: Reg Port map(); Inst3: Reg Port map();  Inst4: Dec Port map(); Inst5: Mux Port map();  So...their names Are not important to define...you can use every module you design..eveywhere...

[Altera_Forum]

--- Quote Start ---  In Vhdl there are not these problems....you can try to create a project_top.vhdl in which you istanziate other sub-modules....mux,decoder,registers...for your custom design....every module can be istanziated many times...even if it has the same name declared in its sub_module.vhdl file For example...  Project-top.vhdl  Reg.vhdl  Dec.vhdl  Mux.vhdl  In Project-top.vhdl you can istanziate Reg.vhdl, for example, there Times  Component Reg Port(); End component;  Component Dec Port(); End component;  Component Mux Port(); End component;    Inst1: Reg Port map(); Inst2: Reg Port map(); Inst3: Reg Port map();  Inst4: Dec Port map(); Inst5: Mux Port map();  So...their names Are not important to define...you can use every module you design..eveywhere...  --- Quote End ---     Thank you for your reply. I believe I understand what you're saying and I think you can do this with the schematic editor as well.  But lets say I've already started a project and I'm working on a sub module deep within a few layers of hierarchy down. When I'm done making edits, I'd like to take that module from within the design and pass it off to someone else. I want to make sure I grab only the files associated with that one module.  Or even the case where I start a module in a brand new project and want to integrate it into an existing project. I need to make sure that the module I'm importing has all unique names. Otherwise my "Reg.vhd" from the module I'm importing will overwrite my "Reg.vhd" I already have defined in the project (Which can have a different meaning/number of bits lets say)

[Altera_Forum]

For VHDL, you don't want to just rename the file, you want to rename the ENTITY inside. Reading two different file names that have the same ENTITY names inside will cause problems(hopefully just an error). When you generate a megafunction, you get to create the name, and it's really important to give it a unique name for its functionality. (But don't make it unique on its instantiaion, since hierarchy will give it a unique name based on where it's instantiated). A good directory structure can help, i.e. something like: 

/rtl  /ingress  /egress  /arbitrator  /common If you write parameterized code, which can be very powerful, you'll find a lot more going into the /common directory.