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07dshaffer
Beginner
71 Views

Creating BSF strips parentheses from output signal size

When I attempt to generate a BSF using the following system verilog code, Quartus 20.1 Prime Lite is stripping the parentheses from the calculation of the output signal size. This results in an incorrect calculation of the size of the output (it is doing 4*2*8+24 = 88). However, it only does this on the BSF (see first attachment). Inside of my module, the size of the signal is correctly calculated as 4*2*(8+24) = 256.

Is this expected behavior for using BSF and BDF files? It's been several years and versions of Quartus since I used a BDF (>10 yrs) rather than doing everything in HDL.

If I use a text editor to edit the BSF file I can change the text to include parentheses and my system compiles (see second attachment). However, as soon I regenerate the BSF it overwrites the old text and is incorrect again.

module sync_adc_data #(
	parameter integer STREAM_COUNT = 4,
	parameter integer CHANNELS_PER_STREAM = 2,
	parameter integer HEADER_WIDTH = 8,
	parameter integer DATA_WIDTH = 24
)
(
	input				clk_i,
	input				rst_i,
	
	output logic [((STREAM_COUNT * CHANNELS_PER_STREAM * (HEADER_WIDTH + DATA_WIDTH)) - 1) : 0]	word_o
);

endmodule : sync_adc_data

 

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2 Replies
NurinaW
Employee
36 Views

Hi,


Sometimes there are problems with generating block symbols from HDL and vice versa. I've reproduced your error and am reporting this issue to engineering.


Regards,

Nurina


NurinaW
Employee
15 Views

Hi,



I'd just like to update you on this matter. Engineering is currently investigating the root cause of the problem.


Regards,

Nurina


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