Creating Flip-flop by using logic gates

[Altera_Forum]

Hi, 

 I am a student who new to VHDL and currently doing VHDL assignment. In this assignment, students are required to create the D, JK flip-flop.   I need help to solve my error for my code as shown as below:   ------------------------ library ieee; use ieee.std_logic_1164.all;  entity Dflip_flop is    port  (  D :in std_logic;  clk :in std_logic;  Q :out std_logic;  Qbar :out std_logic  );   end Dflip_flop;  architecture hc of Dflip_flop is   signal W1 : std_logic;  signal W2 : std_logic;  signal W3 : std_logic;  signal W4 : std_logic;  signal W5 : std_logic;   begin   Q <= W4;  Qbar <= W5;  W1 <= not D;  W2 <= D nand clk;  W3 <= clk nand W1;  W4 <= W2 nand W5;  W5 <= W3 nand W4;    process(clk)  begin   if rising_edge(clk)then   Q <= D;  end if;  end process   end hc; -------------  Error (10500): VHDL syntax error at Dflip_flop.vhd(41) near text "end"; expecting ";", or an identifier ("end" is a reserved keyword)   Can anyone point out what is the syntax error here??  Thanks and appreciated for the helps.

[Altera_Forum]

Besides that, i also faced a prob when designing the JK flip-flop. 

 In this assignment, students are required to simulate the result in the functional and timing mode..  By using the code as shown as below:  ------------- library ieee; use ieee.std_logic_1164.all;  library work;  entity JKflip_flop is    port  (  J :in std_logic;  K :in std_logic;  clk :in std_logic;  Q :out std_logic;  Qbar :out std_logic  );   end JKflip_flop;  architecture hc of JKflip_flop is   signal W1 : std_logic;  signal W2 : std_logic;  signal W3 : std_logic;  signal W4 : std_logic;  signal W5 : std_logic;  signal W6 : std_logic;   begin   Q <= W3;  Qbar <= W4;  W1 <= not (J and clk and W4);   W2 <= not (K and clk and W3);   W3 <= W1 nand W4;  W4 <= W2 nand W3;   end hc;  ----------------  It can only simulate only in the timing mode and it show nothing in the functional mode. I cant find a reason y this will happened??  Anyone knows y tis happened?? Did it need any settings in quartus to make so that it can simulate in the functional mode???  Thank you.

[Altera_Forum]

--- Quote Start ---   Error (10500): VHDL syntax error at Dflip_flop.vhd(41) near text "end"; expecting ";", or an identifier ("end" is a reserved keyword)   Can anyone point out what is the syntax error here??  Thanks and appreciated for the helps.  --- Quote End ---    first of all, you need a semicolon on the end of the "end process" line.  Second of all, you'll have problems with this, as Q has multiple drivers. Q is driven from the process, and from W3. Are you sure you want the process there?  For the second question, what are you similating with? have you written a testbench?

[Altera_Forum]

Hi Tricky, 

 For the 1st question, I will faced the Q is multiple drivers problem if i process there.. Actually i just wan to add on 1 statement in my coding which is " if rising_edge(clk) then  Q <= D" I just have a try to have a process statement in my coding and i don't know where should i put the process statement. Any suggestion??  For the 2nd question, testbench are not written. I just go the simulator settings to set the simulation mode to "functional" and start the vector waveform simulation.

[Altera_Forum]

--- Quote Start ---   For the 1st question, I will faced the Q is multiple drivers problem if i process there.. Actually i just wan to add on 1 statement in my coding which is " if rising_edge(clk) then  Q <= D" I just have a try to have a process statement in my coding and i don't know where should i put the process statement. Any suggestion??   --- Quote End ---    Keep the process - get rid of the logic version (or have a separate output for it). You description of a D-type with a process is correct.    --- Quote Start ---   For the 2nd question, testbench are not written. I just go the simulator settings to set the simulation mode to "functional" and start the vector waveform simulation.  --- Quote End ---    What simulator are you using?

[Altera_Forum]

There was a similar thread few days ago under the same topic "creating flipflops by using logic gates". 

 I will point out that your design defeats the purpose because you are not creating D flop from logic but you are inferring it at:  Q <= D;  thus you might not impress your professor...