Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

Creating a new IP component with VHDL design using a customized library

Altera_Forum
Honored Contributor II
998 Views

Hello, 

 

I am trying to create a new component using Component Editor of Qsys. Actually, the top level design of the new component calls a library "Lib" that I have created and uses a pckage defined in this library. So, in the beginning of the top level design I have: 

 

library Lib; 

use Lib.package.all; 

 

My question is how to tell the Component Editor to take into consideration the library Lib? Shall I add all the library files in the step of specifing the component files? 

 

Thank you,
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
121 Views

Yes, just like if you were to synthesize this in Quartus, you have to add all of your files to the Files tab of the Component Editor.

Altera_Forum
Honored Contributor II
121 Views

I have added all the files if the library "Lib" but I have the same error message. I think that the tool doesn't like user libraries. With Quartus I was able to add all the design files (in VHDL) of "Lib" and to define them as a library then the compilation of the top level design in VHDL was successful. So what I am looking for is how to do the same with QSYS because I can add the files but I don't know how to declare them as library "Lib". 

Thanks.
Reply