Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17259 Discussions

Creating a time delay in Quartus

Altera_Forum
Honored Contributor II
3,753 Views

Hi everyone, 

 

I currently have an fpga design for a nios 2 cyclone 1. I have a signal which comes from a different board and has a frequency of 12.5kHz. I need to create another signal which is phase shifted from this original signal by 4 micro-seconds. 

 

I have tried using a PLL but it tells me the input frequency is out of it's range. Is there a time delay block which I can use? or is there another way to do it? 

 

Any help is greatly appreciated. 

 

Cheers
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
2,625 Views

The usual way is to delay both signal edges by a defined number of system clock cycles, requires a counter an a state machine. Because the delayed signal transitions are at discrete times, you create a delay jitter of +/- 0.5 system clock cycles.

0 Kudos
Reply