Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17259 Discussions

Creating a time delay in Quartus

Altera_Forum
Honored Contributor II
‎07-01-2009 05:58 AM
3,752 Views

Hi everyone, 

 

I currently have an fpga design for a nios 2 cyclone 1. I have a signal which comes from a different board and has a frequency of 12.5kHz. I need to create another signal which is phase shifted from this original signal by 4 micro-seconds. 

 

I have tried using a PLL but it tells me the input frequency is out of it's range. Is there a time delay block which I can use? or is there another way to do it? 

 

Any help is greatly appreciated. 

 

Cheers
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎07-01-2009 06:18 AM
2,624 Views

The usual way is to delay both signal edges by a defined number of system clock cycles, requires a counter an a state machine. Because the delayed signal transitions are at discrete times, you create a delay jitter of +/- 0.5 system clock cycles.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.