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Hi everyone,
I currently have an fpga design for a nios 2 cyclone 1. I have a signal which comes from a different board and has a frequency of 12.5kHz. I need to create another signal which is phase shifted from this original signal by 4 micro-seconds. I have tried using a PLL but it tells me the input frequency is out of it's range. Is there a time delay block which I can use? or is there another way to do it? Any help is greatly appreciated. CheersLink Copied
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The usual way is to delay both signal edges by a defined number of system clock cycles, requires a counter an a state machine. Because the delayed signal transitions are at discrete times, you create a delay jitter of +/- 0.5 system clock cycles.

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