Cryptic warning message when trying to constrain DDR input

[Altera_Forum]

I get the following warning from Quartus II 12.0sp1 when compiling a source synchronous DDR input interface to the FPGA: 

 Warning (176441): The I/O pin adcIn[0] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB )  The PLL is set to source synchronous mode with a 90 degree phase shift. The input min and max delays are set to zero, so this should not be a problem, but even so the timing requirements are not met. Here are the SDC commands I'm using for the DDR inputs:   set_input_delay -clock adcClk-max 0 [get_ports adcIn*] -add_delay set_input_delay -clock adcClk -min -0 [get_ports adcIn*] -add_delay set_input_delay -clock adcClk -max 0 [get_ports adcIn*] -clock_fall -add_delay set_input_delay -clock adcClk -min -0 [get_ports adcIn*] -clock_fall -add_delay  I have no idea what this message means by "in conflict". What is it that is in conflict?

[Altera_Forum]

Try putting some real values in for -max and -min. You've opened up the data valid window to its maximum, so the PLL may be having a hard time trying to figure out how to compensate for this. That's a guess as I've never seen this Warning before.

[Altera_Forum]

Putting real numbers in for the input delay does not make this warning go away. The warning goes away only if the timing requirements are met. So, as far as I can tell, this warning is just telling me that the timing requirements were not achieved, which is kind of useless since the timing report already tells me that.

[Altera_Forum]

How could you not be meeting timing on the inputs with a -max and -min of 0? That basically says you have no external delays, so as long as you clock frequency is within spec, you should be meeting timing.

[Altera_Forum]

The internal delays were too high. Changing the design to use an extra clock phase allowed me to close timing.