Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Custom memory component trouble in SOPC builder

Altera_Forum
Honored Contributor II
‎08-01-2008 12:17 PM
1,189 Views

I just switched to Quartus 7.2 and have a trouble with custom external memory component creation. 

 

First, I started the new component editor and created the Avalon tristate slave and then created a few signals for custom component: 

address [10] (input) 

data [8] (bidir) 

cs_n 

oe_n 

wr_n 

 

The avalon MM tristate bridge was instantiated and connected to NIOS II cpu with internal RAM memory 

 

The custom memory component was connected to 'master' side of that bridge. 

 

No warning were issued and system was generaed OK. 

 

But only data port appeared in top level design !!! 

 

The same works OK in Q 6.1. 

 

Did anybody met this problem? 

 

Regards, 

andrew
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.