I am trying to do some design space exploration for an algorithm implemented in opencl FPGA. Since compiling opencl code for FPGA takes around 4-10 hours, I want some quick performance estimate numbers (cycle approximate). As aoc compiler first does scheduling which is quite fast, I was wondering if there is a way I can generate performance estimates before actually compiling it for FPGA? Is there some tool that I can use?
You just described the single biggest roadblock in using OpenCL on Intel FPGAs. I, for one, have forwarded this very same feedback directly to Intel engineers at least twice, and they claimed other people have also requested this. However, they neither had a solution to this problem back then, nor does any solution that I am aware of exist now. Apparently it is possible to perform modelsim-based simulations if you use the HLS compiler (I haven’t tested it personally), though just for the module you describe using HLS and not the whole system. For OpenCL, considering the fact that it is next to impossible to simulate signals related to PCI-E and DDR memory with any reasonable accuracy, I doubt any proper performance estimation solution will ever be made.