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Hi
I'm making a design in which I'm seeing some strange differences between the compiler report and what it's seen in the Chip Planner: In the Compiler report, the use of LABs reaches a 100%, but in the Chip Planner there are obviously a lot of unused LABs (the light blue cells near the top border and all the southern zone in the attached picture) http://www.alteraforum.com/forum/attachment.php?attachmentid=11053&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11054&stc=1 The problem is that when I add more blocks to my design, the fitter starts failing (it says it needs to use more LABs than the device contains), but it seems to me that there should be still enough space in this device... Am I missing something? Thanks! (Cyclone V, compiled with Quartus II 15.0)Link Copied
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Might be some bug with the Chip Planner. Probably you should raise a tiket to Altera support on this to clarify.
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You use 74% of ALM, like report say
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Hi,
Well, what I'm more concerned about is the use of LABs... Each LAB contains 10 ALMs, and according to the Chip Planner, about the 25% southern LABs are completely empty (and given that most of the used ones in the center of the layout are just half-used, that 74% of ALMs still seems too much too me) I still don't see how are the report numbers related to the Chip Planner actual results.- Mark as New
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Maybe you are saturating LAB interconnections so Quartus can't use all ALM? Could you share your design?
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I can't really share the design, but I'll start by checking the interconnections usage, if that unused LABs are unreachable that would explain the problem. Thanks!

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