Cyclone V Gate-Level simulation

[Alberto_G]

Hi all,

I'm trying to perform a gate-level functional simulation using a FPGA from the Cyclone V family (I know that gate-level + timing simulations are not suported for this type of FPGA), after compiling the design, Quartus generates the .vho file that is needed to run this type of simulation, however, after compiling this file together with the testbench file on ModelSim and running the simulation I don't get any results and all the outputs remain at 0, does anyone know why?

This is the information I found regarding this topic:

https://www.intel.com/content/www/us/en/docs/programmable/683080/18-1/simulation-levels.html

[ShengN_Intel · Accepted solution]

Hi,

Make sure you're following the steps shown in this video https://www.youtube.com/watch?v=HFWd7QPibMY&t=476s

Make sure also there's no problem with the testbench.

Attached a minimal sample design on gate-level simulation and respective script.

Thanks,

Regards,

Sheng