Cyclone V SerDes performance and ADC characteristic

[Altera_Forum]

Hi all, 

 please help me interpreting this specification from Cyclone V data spec. It says that the max. RX SerDes data rate is 875 Mbps @ 350 ps sampling window right ? Is that a minimal sampling window acceptable by FPGA constraints ? Or maybe I can decrease the sampling window with a better design/skew and achieve higher data rates ? (I'm trying to achieve 1Gbps)   https://www.alteraforum.com/forum/attachment.php?attachmentid=6467    Another question. What are the crucial parameters of an ADC which determine the minimal sampling window. (http://www.hittite.com/content/documents/data_sheet/hmcad1511.pdf) Is that the Data rise- and fall time 20% to 80 % ?   Best regards Joel

[Altera_Forum]

Hi Joel, 

  --- Quote Start ---   please help me interpreting this specification from Cyclone V data spec. It says that the max. RX SerDes data rate is 875 Mbps @ 350 ps sampling window right ? Is that a minimal sampling window acceptable by FPGA constraints ? Or maybe I can decrease the sampling window with a better design/skew and achieve higher data rates ? (I'm trying to achieve 1Gbps)   --- Quote End ---    The specification is likely the maximum. This will be enforced by Quartus, so you would not be able to try using the interface at 1Gbps anyway - although if you manually configured the PLL, you probably could get it running at whatever frequency you like.    --- Quote Start ---   Another question. What are the crucial parameters of an ADC which determine the minimal sampling window. (http://www.hittite.com/content/documents/data_sheet/hmcad1511.pdf) Is that the Data rise- and fall time 20% to 80 % ?    --- Quote End ---    What mode do you plan on operating this ADC in? If you want 1GHz sampling frequency, this part uses interlacing of 4 cores. Interlacing cores generates artifacts that you might not be able to deal with. If you want 1GHz sampling rate parts, e2v and National Semiconductor (now part of TI) have parts.  Browse through the documents here for a design that uses the e2v part.  http://www.ovro.caltech.edu/~dwh/carma_board/  This design used Stratix II FPGAs. The SERDES interfacing is discussed in  http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf  Note that the e2v part has a demux-by-2 output, so 500Mbps output data rate. You can interface that to the Cyclone V easily enough. Just duplicate what it done in these documents.  Cheers, Dave

[Altera_Forum]

Thank you for response. It looks like I have to design for Arria V instead of Cyclone V. That's a very bad information. 

 I actually intend to use the ADC in Quad Channel Mode. I want to connect 2 antennas after demodulation that is with I/Q separated (250MHz baseband bandwidth).

[Altera_Forum]

--- Quote Start ---  Thank you for response. It looks like I have to design for Arria V instead of Cyclone V. That's a very bad information.  I actually intend to use the ADC in Quad Channel Mode. I want to connect 2 antennas after demodulation that is with I/Q separated (250MHz baseband bandwidth).  --- Quote End ---    Do you have to use this particular Hittite part? There are other ADCs out there that clock at this rate. Perhaps one with a JESD204 (serdes) interface?  Look at the devices from Texas Instruments and NXP. Analog devices also has fast ADCs.  The e2v part I referred you to can be operated as dual-channels at 1GHz clock rate. You could operate the device at 1GHz clock rate, operate in 1:2 output data demux mode, and receive 16-bits at 500Mbps, or you could operate it at 500MHz clock rate in 1:1 output mode and receive 8-bits and 500Mbps per channel.  Cheers, Dave

[Altera_Forum]

Hello Dave,  

 in the meantime I was analyzing the possibilities regarding another ADCs. There is however one thing that I need to clear first. Could I implement 3.125 Gbps transceivers (Cyclon V GX) as a SerDes interface for the HMCAD 1511 ADC ? I don't have any experiences implementing transceivers but it looks promising. What do you think ?  Best reagrds Joel

[Altera_Forum]

Hi Joel, 

  --- Quote Start ---   in the meantime I was analyzing the possibilities regarding another ADCs. There is however one thing that I need to clear first. Could I implement 3.125 Gbps transceivers (Cyclone V GX) as a SerDes interface for the HMCAD 1511 ADC ? I don't have any experiences implementing transceivers but it looks promising. What do you think ?   --- Quote End ---    Don't bother trying to interface using the transceivers. High-speed transceivers are not just "faster" LVDS channels.  FPGA LVDS channels can be used to interface to an ADC like this Hittite part because a group of LVDS receivers can be used synchronously per the document I referred you to above.  FPGA SerDes receivers are essentially independent entities. They like to be operated in lock-to-data mode, where the clock is recovered from the data. This means that the data has to be modulated such that it has enough transitions that the clock can be recovered and the receiver PLL can remain locked.  I'm currently developing an interface to the Hittite 20GHz ADC  http://www.hittite.com/products/view.html/view/hmcad5831lp9be  using 10Gbps Stratix IV GT transceivers ... and its not a "simple" problem :)  Cheers, Dave