DCFIFO/FIR Compiler Data Processing Error

[Altera_Forum]

Hello,

I am working on a design which takes an input impulse signal and passes it through to a Cyclone III FPGA via an ADC (LTC2253) and I cannot get the appropriate signals passing through to my storage. When I compile my code it compiles OK, but I lose over 1100 registers on synthesis, primarily from my FIR filter due to the data_in port being stuck at ground. 

How can I determine what the cause of this problem is and how can I resolve it? I have noticed in my waveforms (both obtained from an oscilloscope and from signaltap) that my rdempty line is always high for my FIFO, and my source valid is always staying low from my FIR. 

I am using Quartus version 13.1 and both the FIFO and the FIR filter were implemented using the megafunction wizard.

Any help is much appreciated!

My code is below;

...

input Clk;

input [11:0]ADC_Data;

input ADC_Data_OF;

input CPU_Clear;

input CPU_Read_Clk;

input CPU_Read_Rq;

input CPU_Trigger;

output [7:0]CPU_Data;

output FIFO_RD_Empty;

output FIFO_WR_Full;

output FIFO_WR_Empty;

output SamplingClockFIFO;

// Define local constants.

parameter STATE_START = 8'h00;

parameter STATE_SKIP_SAMPLES = 8'h01;

parameter STATE_COLLECT_SAMPLES = 8'h02;

parameter STATE_WAIT_FOR_HOST_RESET = 8'h03;

parameter STATE_MACHINE_RESET = 8'hFF; // Go to the default of the case statement. This will keep the reset

// code in one location.

parameter SAMPLES_TO_SKIP = 5; 

parameter ADC_OFFSET = 12'h7FF; 

// Define registers.

reg EnableFilter = 1'b0;

reg ADC_Data_Sink_Valid = 1'b0;

reg SamplingTriggeredFIFO = 1'b0;

reg SamplingTriggeredFilter = 1'b0;

reg [1:0]Sink_Error;

reg [7:0]StateMachineCounter = STATE_START;

reg [7:0]CPU_Data;

reg [15:0]ADC_Data_To_FIFO;

reg [3:0]SkipSampleCounter;

reg [11:0]ADC_Data_To_Filter;

// Define interconnects.

wire [7:0]Data_To_CPU;

wire SamplingClockFilter;

wire FIFO_Not_Full;

wire [29:0]Source_Data;

wire Sink_Ready;

wire Source_Valid;

wire [1:0]Source_Error;

wire Filter_Reset_n;

wire nCPU_Clear;

// Define Logic.

not NOT0(FIFO_Not_Full, FIFO_WR_Full);

not NOT1(Filter_Reset_n, CPU_Clear);

//not NOT2(nCPU_Clear, CPU_Clear);

assign SamplingClockFIFO = (SamplingTriggeredFIFO == 1'b0) ? 1'b0 : Clk;

assign SamplingClockFilter = (SamplingTriggeredFilter == 1'b0) ? 1'b0 : Clk;

// Instantiate the filter

fir_highpass Filter0(.clk(SamplingClockFilter), .reset_n(Filter_Reset_n), .enable(EnableFilter), .ast_sink_data(ADC_Data_To_Filter), 

.ast_sink_valid(ADC_Data_Sink_Valid), .ast_source_ready(FIFO_Not_Full), .ast_sink_error(Sink_Error), 

.ast_source_data(Source_Data), .ast_sink_ready(Sink_Ready), .ast_source_valid(Source_Valid), 

.ast_source_error(Source_Error));

// Instantiate the FIFO.

FIFO Data_Storage(.aclr(CPU_Clear), .data(ADC_Data_To_FIFO), .rdclk(CPU_Read_Clk), .rdreq(CPU_Read_Rq), 

.wrclk(SamplingClockFIFO), .wrreq(Source_Valid), .q(Data_To_CPU), .rdempty(FIFO_RD_Empty),

.wrempty(FIFO_WR_Empty), .wrfull(FIFO_WR_Full));

// Define how the data is to be written to the FIFO.

always @(posedge Clk)

begin

// If the CPU commands the FIFO to clear, then reset the State Machine.

if(CPU_Clear == 1'b0)

begin

StateMachineCounter = STATE_MACHINE_RESET; 

end

case(StateMachineCounter)

STATE_START:

begin

// Determine if the CPU has started a surge and the FIFO is empty.

if((CPU_Trigger == 1'b1) && (FIFO_WR_Full == 1'b0))

begin

// Signal that the CPU has started a surge.

SamplingTriggeredFIFO = 1'b1;

SamplingTriggeredFilter = 1'b1;

// Zero the skip sample counter.

SkipSampleCounter = 4'b0;

// Move to the next state.

StateMachineCounter = StateMachineCounter + 1;

end

end

STATE_SKIP_SAMPLES:

begin

// Increment the counter to skip the correct number of samples.

SkipSampleCounter = SkipSampleCounter + 1;

if(SkipSampleCounter >= SAMPLES_TO_SKIP)

begin

// Move to the next state.

StateMachineCounter = StateMachineCounter + 1;

// Signal that the sample values are now valid.

ADC_Data_Sink_Valid = 1'b1;

// Enable the filter for accepting data.

EnableFilter = 1'b1;

// Indicate to the filter that there is not an error in the data.

Sink_Error[1:0] = 2'h0;

end

end

STATE_COLLECT_SAMPLES:

begin

if(FIFO_WR_Full == 1'b0)

begin 

// Determine if the ADC has overflowed.

if(ADC_Data_OF == 1'b0)

begin

// Indicate to the filter that there is not an error in the data.

Sink_Error[1:0] = 2'h0;

// Subtract the ADC offset from the ADC data value. This will allow

// the signed fractional coefficients and the filter to do its job.

ADC_Data_To_Filter[11:0] = ADC_Data[11:0] - ADC_OFFSET;

if(Source_Valid == 1'b1)

begin 

ADC_Data_To_FIFO[15:12] = 4'h0;

ADC_Data_To_FIFO[11:0] = Source_Data[22:11];

ADC_Data_To_FIFO[11:0] = ADC_Data_To_FIFO[11:0] + ADC_OFFSET;

end

else

begin

ADC_Data_To_FIFO[15:0] = 16'h0000;

end

end

else

begin

ADC_Data_To_FIFO[15:0] = 16'h0FFF;

end

end

else

begin

// Move to the next state.

StateMachineCounter = StateMachineCounter + 1;

ADC_Data_To_Filter[11:0] = 12'h000;

// Stop the FIFO from accepting any new data.

SamplingTriggeredFIFO = 1'b0;

end

end

STATE_WAIT_FOR_HOST_RESET:

begin

// Wait for the CPU to signal that the FIFO is to be cleared. 

if(CPU_Clear == 1'b1)

begin

// Move to the next state.

StateMachineCounter = StateMachineCounter + 1;

// Stop the clock cycles to the filter here.

SamplingTriggeredFilter = 1'b0;

// Disable the filter.

EnableFilter = 1'b0;

end 

end

default:

begin

StateMachineCounter = STATE_START;

SamplingTriggeredFIFO = 1'b0;

SamplingTriggeredFilter = 1'b0;

EnableFilter = 1'b0;

ADC_Data_To_FIFO[15:0] = 16'hFFFF;

ADC_Data_To_Filter[11:0] = 12'h000; 

ADC_Data_Sink_Valid = 1'b0;

Sink_Error[1:0] = 2'h0;

end

endcase

end

always @(posedge CPU_Read_Clk) 

begin

// While there is a CPU read request and the FIFO is not empty, allow the data to be put on the bus.

if((CPU_Read_Rq == 1'b1) && (FIFO_RD_Empty == 1'b0))

begin

// Place the high byte onto the bus first. 

CPU_Data[7:0] = Data_To_CPU[7:0];

end

else

begin

// Setup a default value to the CPU data port.

CPU_Data[7:0] = 8'hFF;

end

end

endmodule