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DCFIFO_MIXED_WIDTH simulation incorrect

SStär
Beginner
838 Views

According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2).

 

Figure 7 and 8 show write and read transaction for 16 to 8 and 8 to 16 bit interfaces as I'd expect it.

 

When I instantiate a DCFIFO_MIXED_WIDTHS with Quartus 18.1 (18.1.0 222 or 18.1.2 277) and with those options, the simulation (Questa Sim 64 10.6e - and also Modelsim) doesn't show the expected behaviour though:

For 8 bit write, 16 bit read, the upper 8 bits of the words read are all zeros. In the inverse case, the output word is always the lower part of the input word - and rdusedw and wrusedw also don't behave like in the figures.

 

I have attached a screenshot of my simulation for the 8 bit write, 16 bit read case.

 

Are there any special settings to be done when instantiating it via the dcfifo_mixed_widths primitive?

 

(the target is a Stratix 10, but the same behaviour also shows for the Arria 10 as target)

 

Thanks in advance, Steffen

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9 Replies
Kenny_Tan
Moderator
196 Views
can u attached your design.qar here to have a look?
SStär
Beginner
196 Views

Hi again,

so I have very carefully checked again the settings (generics) when instantiating the dcfifo_mixed_widths and figured that this "feature" is related to the "intended_device_family" generic.

If I set this to "UNUSED", I get the behaviour as described, if I set it to "Arria 10" or "Stratix 10", then the FIFO behaviour is as expected.

 

Please let me know if that is an intended feature. I aim at a very generic implementation where also the device is set as a generic and might be undeterminded ("UNUSED"), but of course, I'd still like the simulation to show the correct behaviour.

 

Thanks and tschö, Steffen

SStär
Beginner
196 Views

Dear @KennyT_Intel​ ,

 

sorry to bug you again, but what's your feedback on my finding?

 

An acceptable option for me would be to not go for "UNUSED" in case I don't know which device is targeted, but any device that is supported by default with the Quartus suite [that has dcfifo mixed width capabilities] (without the need to install any particular device support package).

 

Thanks and tschö, Steffen

Kenny_Tan
Moderator
196 Views

Hi, what you can do is try on Gate level simulation to see the behavior. If it is intended_device_family, there is a high chance it is not supported.

Kenny_Tan
Moderator
196 Views
  1. To run the functional gate level simulation Click More EDA Netlist Writer Settings. The More EDA Netlist Writer Settings dialog box appears. In the Existing options settings list, click Generate netlist for functional simulation only and select On from the Setting list under Options.

 

Kenny_Tan
Moderator
196 Views
any update?
SStär
Beginner
196 Views

Dear @KennyT_Intel​ ,

 

so I was checking my Quartus installation up and down, but I don't have this "Generate netlist for functional simulation only" in the settings list.

No matter which Simulation tool name I select, the only 5 settings are "Architecture name in VHDL output netlist", "Bring out device-wide set/reset signals as ports", "Do not write top level VHDL entity", "Flatten buses into individual nodes" and "Truncate long hierarchy paths". These are all set to "Off", except the first which is set to "structure".

 

I made some further tests for intended_device_family: E.g. setting it to "Cyclone IV" in case I don't know what it will be, seems to work (even if I don't have any Cyclone devices installed.

That is an acceptable work-around for me.

 

Tschö, Steffen

Kenny_Tan
Moderator
196 Views
As long as you are simulating vo or vho files, you are simulating the netlist. It is not under simulation, it is under Quartus assignmnet -> settings.
Kenny_Tan
Moderator
196 Views
I mean it is not under installation
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