Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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DDR2 HPCII v11.0 problem, thanks for help !

Altera_Forum
Honored Contributor II
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everything seems well, however, local_init_done is always low, what's wrong?  

I tried both the full calibration and "skip the calibration", it doesn't change anything, the local_init_done is always low ! 

PS. I believe the PCB board is good. 

 

PS. I tried to use debug toolkit to check the internal states, however, when I downloaded  

altera.com/technology/memory/dram/altmemphy/debug/debug-toolkit.zip 

 

and un-packed it, there is a DEBUG GUI README.txt, which says: This is the Altera ALTMEMPHY Debug GUI. It is an application to view the internal state of the calibration sequencer that initialises the DDR3 ALTMEMPHY Megafunction. 

 

But mine memory is DDR2 ! 

 

PS. ctl_cal_fail is high and ctl_cal_success is low, what's wrong with the calibration? 

 

PS. the memory is sumsung K4T51163QI
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Altera_Forum
Honored Contributor II
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check if You've connected reset pins properly. Probably You've missed reset and reset_n pins.

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Altera_Forum
Honored Contributor II
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Thanks ! There are "global_reset_n" and "soft_reset_n" in the module of DDR2 controller, is there any specification on the duration length of these two "reset_n" ?

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Altera_Forum
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Can anybody please answer this? I am having teh same problem. 

 

Is there any specification for the global and soft reser 

I have connected global to 2ms low pulse, and soft is always high 

Calibration does not pass for me either
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Can anybody please answer this? I am having teh same problem. 

 

Is there any specification for the global and soft reser 

I have connected global to 2ms low pulse, and soft is always high 

Calibration does not pass for me either 

--- Quote End ---  

 

 

Did you check your schematic? Is the memory connected properly? The design synthesizes and passes timing fine?
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Altera_Forum
Honored Contributor II
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Yes. I stole the schematics from an earlier working design with Cyclone II/DDR2. All timing passed. 

I am using ALTMEMPHY, Cyclone IV and DIMM-240 1G (unbuffered) 

Calibration does not pass. 

Also, I can not find the debug_toolkit for external memory testing. Looks like Altera has removed it. Can you please attach it here, if you have it
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Altera_Forum
Honored Contributor II
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And does it start calibration at all? Did you check your termination and reference voltages? Did you do length matching on the tracks?

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Altera_Forum
Honored Contributor II
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Yes I can see activity on DQ/DQS at the startup on oscilloscope, so it does do something.. but fails (local_init_done does not go high) 

 

Yes length matching was done as per DDR2 requirements (~3.5"). Clocks are routed differentially 

 

Could it be reset? I am just trying double registering asynchronous. 

 

Can you please look at attached schematics. 

-- I used phy_clk (125Mhz) as my application clock to read/write from ALTMEMPHY. Is this OK?
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Altera_Forum
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All slacks are positive 

 

Info: Address Command (Fast 1200mV 0C Model) | 4.831 1.662 

Info: DQS vs CK (Fast 1200mV 0C Model) | 1.658 1.735 

Info: Mimic (Fast 1200mV 0C Model) | 3.017  

Info: Phy (Fast 1200mV 0C Model) | 3.017 0.145 

Info: Phy Reset (Fast 1200mV 0C Model) | 5.174 0.488 

Info: Read Capture (Fast 1200mV 0C Model) | 0.807 0.812 

Info: Write (Fast 1200mV 0C Model) | 0.796 1.077
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Altera_Forum
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Please see attached. This is Altera example driver with ALTMEMPHY for DDR2 memory 

 

Even with "Skip Calibration" it never ends. It ran all night and only reached 12ms. Look at the result. It only wrote 0x00 and 0xFF in the begining, and then DQ and DQS were inactive for the rest. Test Complete never went high. What is it waiting for? 

 

Does this give anybody any clue? I must be doing something very basic wrong
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Altera_Forum
Honored Contributor II
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Did you regenerate qsys system after changing settings to no calibration? 

Are you setting all resets correctly?
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Altera_Forum
Honored Contributor II
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I am not using Qsys. I am using MegaWizrad to generate ALTMEMPHY with example driver. I have connected the top level (example driver) clock_source and global_reset_n to the correct pin appropriately.  

 

-- Calibration fails with or without DIMM installed. Memory stick absence create no difference in behavior 

-- Clocks are differential and at 125Mhz 

-- There is some initial activity on DQ/DQS channels, but they die off (at every reset) 

-- local_init_done stays low 

-- Signal tap shows a single write with some random words, but "ready" never gets asserted (at every reset) 

-- Signal tap shows that Calibration_fail gets asserted at every reset 

-- ModelSim shows just a blip on DQ/DQS attempting to write all 0s and all 1s pattern, then they are tristate forever 

-- Modelsim runs forever (overnight), but test_complete never goes high, and I dont see any activity on DQ/DQS after a initial blip (see attached)
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Altera_Forum
Honored Contributor II
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For the DIMM properties, are you using a preset? Which version of Quartus you are using?

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Altera_Forum
Honored Contributor II
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I used Quartus 11.1, 13.0 and now 15.0. All same results. 

 

Yes I am using my own PRESET, stolen from a design that worked for Cyclone II 8 years back. I am thinking that could be a problem. Do you have a PRESET for 1GB/2GB unbuffered DDR2? Thanks, I really appreciate your answers. 

 

I get two warnings from ALTMEMPHY: 

 

warning: Cannot meet tRTP requirement of 7.5 ns. For a Memory interface clock frequency of 125.0 MHz, the minimum is 8.8 ns.  

warning: Cannot meet tRRD requirement of 7.5 ns. For a Memory interface clock frequency of 125.0 MHz, the minimum is 8.8 ns.  

 

I checked Micron data sheets they are both 7.5ns. I dont know why Cyclone IVE-8 can not meet the timings
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Altera_Forum
Honored Contributor II
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I think some presets should already be there. If you've taken old presets it might be a problem of changed variables or other things. Either try to find existing preset or reset everything and fill in according to JEDEC standards. 

Also, I wonder... UniPHY is not supported for your device?
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Altera_Forum
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Yes, UniPHY is not supported for Cyclone IV. 

Currently, I am trying a JEDEC standard DDR2 1GB DIMM. I will post the result
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Altera_Forum
Honored Contributor II
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JEDEC standard 1GB preloaded by Altera failed as well

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Altera_Forum
Honored Contributor II
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Failed in simulation or hardware? 

I would offer two things then: 

1) If it fails in hardware -> check pinout. 

2) Raise a Service Request and send them your archived project (.qar) 

 

Also have a look at example projects of development kits. For example: 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=142&no=513 

or 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=260 

 

I think Arria II or Stratix III are old enough to have project examples with ALTMEMPHY. 

 

Are you using full rate bridge or half rate bridge?
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Altera_Forum
Honored Contributor II
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Failed in simulation or hardware? in hardware. simulation never finishes, it runs forever 

 

I would offer two things then: 

1) If it fails in hardware -> check pinout. i did. they all match with schematics 

2) Raise a Service Request and send them your archived project (.qar). yes i have it open: 11185961 

 

 

Are you using full rate bridge or half rate bridge? full rate
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