DE2-70 SOPC SDRAM compile error

[Altera_Forum]

Hi. 

 I study with DE2-70 & "using the sdram memory on altera's de2-70 board with verilog design" manual.   I practiced sopc & sdram example but i had some error messages as shown in the attached image.   I assigned the pin map by importing "de2-70 pin assignments.csv" file, and coded verilog source file using pin node name.   please let me how can i solve this problem..   Thanks in advance.   https://www.alteraforum.com/forum/attachment.php?attachmentid=2873    https://www.alteraforum.com/forum/attachment.php?attachmentid=2874

[Altera_Forum]

I do not programm in Verilog, but from my understanding the datapins should be bidirectional?! (you can read it in the sopc description: "dq to and from the...") I think the instanciation for that in verilog is "inout [15:0] dram_dq;" perhaps give it a try, but I am not sure. 

 Have a nice day, Peter.

[Altera_Forum]

--- Quote Start ---  I do not programm in Verilog, but from my understanding the datapins should be bidirectional?! (you can read it in the sopc description: "dq to and from the...") I think the instanciation for that in verilog is "inout [15:0] dram_dq;" perhaps give it a try, but I am not sure.   Have a nice day, Peter.  --- Quote End ---     I didn't find my mistake about "inout" & "input".. Thanks for your apply!