DMA with simple custom IP created by QSYS

[Altera_Forum]

I have a simple custom IP integrated into QSYS with Avalon-MM slave interface. I did so by using Component Editor.  

The IP has one register, by reading this multiple times the IP provides series of data to master. In that sense, this IP is similar to FIFO.   Reading this register from Nios-II CPU (or system consol) appears working OK.  But with a simple Nios-II program, I tried DMA. This IP is connected to read-master of DMA controller (the write-master is on-chip RAM).    When I did DMA, it finishes as expected but the data from the custom IP is not expected.  After looking at signalTAP signals, during whole DMA period, the following signals from master remains unchanged.   1) chipselect = stay '1' 2) read= stay '1'  3) address = stay constant (as expected)    The custom IP I'm using need to detect the boundary of every transfer (i.e., every read request), so that it presents valid data for every read request (like reading data from FIFO).  As I look at Avalon Interface manual, my understanding is that this is correct behavior of Avalon-MM slave signals. So, I'm a bit stuck.   Then, here is my question. In this case, do I need to use "begintransfer" signal (most likely as replacement of chipselect signal)?  My custom IP has 1 wait-time (hence read cycle is 2 clocks). Under this condition, I think I can use "begintransfer" signal as indication of new read request in combination with "read" signal.    Thank you for your help, in advance.   p.s., In this case, I'm not using burst tranfer. And I'm not using "waitrequest" signal because constant 1 read-wait is sufficient for this simple IP.

[Altera_Forum]

Hi, 

 my experience whith Altera IPs is that you have to implement the same Avalon protocol in your custom IP just like the connected Altera IP. I'm using SGDMA controller in burst mode. The connected custom IP must use the signals read, readdatavalid, readdata, beginbursttransfer, waitrequest and burstcount (or size).  Best regards Jens