DS18b20+VHDL

[Altera_Forum]

Hi all,

I need a little help with my design,I would like connect sensor ds18b20 to the FPGA Altera DEOshematic.jpg I use the internal clock50MHz,I wrote some code but my design doesn't work.shows the maximum temperature , I did oscilloscope measurementsosc.jpg I have signal puls from the ds18b20. probably I wrote bad read and write slots time code.

I don't know how to improve it.

My code:

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_ARITH.ALL; 

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

LIBRARY altera_mf;

USE altera_mf.all;

entity blok is 

port 

( 

clk50m: in std_logic; 

temper: out std_logic_vector(15 downto 0); 

wireout: inout std_logic 

); 

end blok;

architecture Behavioral of blok is 

type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,w0,w3,w1,w2,read0,read1,r ead2,read3); 

signal state: state_type;

signal temp: std_logic_vector( 15 downto 0); 

signal reset: std_logic; --variable in time 

signal i: integer range 0 to 50000000;

begin 

temper<= temp; 

process(clk50m) 

variable j : integer range 0 to 15; 

variable flag : integer range 0 to 60; 

begin 

if rising_edge(clk50m) then 

case state is 

when s0 => --initialization ds18b20 

wireout<='0'; -- 0 on output

reset<='1'; 

state<=s1; 

when s1 => 

reset<='0'; 

if(i=25000) then --wait 500us 

wireout<='Z'; --Z on output 

reset<='1'; 

state<=s2; 

end if; 

when s2 => 

reset<='0'; 

if (i=5000) then --wait 100us 

reset<='1'; 

state<=s3; 

end if; 

when s3 => 

if(wireout='0') then --check signal from the ds18b20 

state<=s4; 

elsif(wireout='1') then --if none, back to top (s0) 

state<=s0; 

end if; 

when s4 => 

reset<='0'; 

if(i=20000) then --wait 400us 

reset<='1';

state<=s5;

end if; 

when s5 => --

--sending a command CCxh

if (flag = 0 ) then flag:=1;state <=w0; 

elsif (flag = 1 ) then flag:=2;state <=w0; 

elsif (flag = 2 ) then flag:=3;state <=w2;wireout<='0'; 

elsif (flag = 3 ) then flag:=4;state <=w2;wireout<='0'; 

elsif (flag = 4 ) then flag:=5;state <=w0; 

elsif (flag = 5 ) then flag:=6;state <=w0; 

elsif (flag = 6 ) then flag:=7;state <=w2;wireout<='0'; 

elsif (flag = 7 ) then flag:=8;state <=w2;wireout<='0'; 

--sending a command 44xh 

elsif (flag = 8 ) then flag:=9 ;state <=w0; 

elsif (flag = 9 ) then flag:=10;state <=w0; 

elsif (flag = 10 ) then flag:=11;state <=w2;wireout<='0'; 

elsif (flag = 11 ) then flag:=12;state <=w0; 

elsif (flag = 12 ) then flag:=13;state <=w0; 

elsif (flag = 13 ) then flag:=14;state <=w0; 

elsif (flag = 14 ) then flag:=15;state <=w2;wireout<='0'; 

elsif (flag = 15 ) then flag:=16;state <=w0; 

elsif (flag = 16 ) then flag:=20;state <=s6;wireout<='Z'; 

--sending a command CCxh

elsif (flag = 20 ) then flag:=21;state <=w0; 

elsif (flag = 21 ) then flag:=22;state <=w0; 

elsif (flag = 22 ) then flag:=23;state <=w2;wireout<='0'; 

elsif (flag = 23 ) then flag:=24;state <=w2;wireout<='0'; 

elsif (flag = 24 ) then flag:=25;state <=w0; 

elsif (flag = 25 ) then flag:=26;state <=w0; 

elsif (flag = 26 ) then flag:=27;state <=w2;wireout<='0'; 

elsif (flag = 27 ) then flag:=28;state <=w2;wireout<='0'; 

--sending a command BExh

elsif (flag = 28 ) then flag:=29;state <=w0; 

elsif (flag = 29 ) then flag:=30;state <=w2;wireout<='0'; 

elsif (flag = 30 ) then flag:=31;state <=w2;wireout<='0'; 

elsif (flag = 31 ) then flag:=32;state <=w2;wireout<='0'; 

elsif (flag = 32 ) then flag:=33;state <=w2;wireout<='0'; 

elsif (flag = 33 ) then flag:=34;state <=w2;wireout<='0'; 

elsif (flag = 34 ) then flag:=35;state <=w0; 

elsif (flag = 35 ) then flag:=36;state <=w2;wireout<='0'; 

--s7 

elsif (flag = 36 ) then flag:=40;state <=s7; 

end if; 

when s6 => 

reset<='0'; 

if (i = 37500000 or wireout='1' ) then --wait 750ms 

state <= s0; 

reset<='1'; -- 1 on output

end if; 

when s7 => --odczyt temperatury

if (flag = 40 ) then flag:=41; state<=read0;j:=0; wireout<='0'; 

elsif (flag = 41 ) then flag:=42; state<=read0;j:=1; wireout<='0'; 

elsif (flag = 42 ) then flag:=43; state<=read0;j:=2; wireout<='0'; 

elsif (flag = 43 ) then flag:=44; state<=read0;j:=3; wireout<='0'; 

elsif (flag = 44 ) then flag:=45; state<=read0;j:=4; wireout<='0'; 

elsif (flag = 45 ) then flag:=46; state<=read0;j:=5; wireout<='0'; 

elsif (flag = 46 ) then flag:=47; state<=read0;j:=6; wireout<='0'; 

elsif (flag = 47 ) then flag:=48; state<=read0;j:=7; wireout<='0'; 

elsif (flag = 48 ) then flag:=49; state<=read0;j:=8; wireout<='0'; 

elsif (flag = 49 ) then flag:=50; state<=read0;j:=9; wireout<='0'; 

elsif (flag = 50 ) then flag:=51; state<=read0;j:=10;wireout<='0'; 

elsif (flag = 51 ) then flag:=52; state<=read0;j:=11;wireout<='0'; 

elsif (flag = 52 ) then flag:=53; state<=read0;j:=12;wireout<='0'; 

elsif (flag = 53 ) then flag:=54; state<=read0;j:=13;wireout<='0'; 

elsif (flag = 54 ) then flag:=55; state<=read0;j:=14;wireout<='0'; 

elsif (flag = 55 ) then flag:=60; state<=read0;j:=15;wireout<='0'; 

elsif (flag = 60 ) then flag:=0;state<=s0; 

end if; 

--write

when w0 => 

wireout<='0'; --Set 0 to wireout

reset<='0'; 

if (i = 4000) then --wait 80us 

wireout<='Z'; --Set Z to wireout

reset<='1'; 

state<=w1; 

end if; 

when w1 => 

state<=s5; --back after setting 1

when w2=> 

state<=w3; --go to state w1

when w3 => 

wireout<='1'; --send 1

reset<='0'; 

if (i = 4000) then --wait 80us 

reset<='1'; 

state<=s5; 

end if; 

--reading

when read0=> 

state <= read1; --go to reading 

when read1=> 

wireout <= 'Z'; --Set Z to wireout 

reset<='0'; 

if (i = 500) then --wait 10us 

reset<='1'; 

state <= read2; 

end if; 

when read2=> 

temp(j)<= wireout; --read bit temperature 

state <= read3; 

when read3=> 

reset<='0'; 

if (i = 2750) then --wait 55us 

reset<='1'; 

state <= s7; 

end if; 

--

when others => 

state <=s0; 

end case; 

end if; 

end process; 

process(clk50m,reset) 

begin 

if (reset='1')then 

i<=0; 

elsif rising_edge(clk50m) then 

i<=i+1; 

end if; 

end process; 

end Behavioral;

[Altera_Forum]

How did you test this code? have you written a testbench?

[Altera_Forum]

I only programming my boar DE0 and measured Inout signal in the oscilloscope ,The resulting vector was displayed in the diodes. I don't know where I got problem in my code..

[Altera_Forum]

Then I suggest writing a testbench and running simulations

[Altera_Forum]

I did testbench in ModelSim-Altera works well ,but in the real system isn't working.

[Altera_Forum]

How do you mean "Works well"? Does it follow the spec of the ds18b20?

[Altera_Forum]

--- Quote Start ---  I did testbench in ModelSim-Altera works well ,but in the real system isn't working.  --- Quote End ---    if your counter(i) is meant to go up to 50000000 then rollover then you are not doing that. You left it free running

[Altera_Forum]

yes it's true because I have clock 50MHz(20ns) but i have resest: 

 begin   if (reset='1')then   i<=0;   elsif rising_edge(clk1m) then   i<=i+1;   end if;   I think that did it well.

[Altera_Forum]

But when is that reset asserted? Is it before the counter gets to 50000000? In simulation, if it went over 50mil, you would get an error (but hardware will just roll over - creating a hardware simulation missmatch). 

 If you use signal tap and find the counter is going over 50mil, you need to go back and re-run your simulations.