DSP usage issue with arria10

Altera_Forum · ‎02-25-2016

The following circuit is designed to fit in 2 DSPs on StratixV FPGA:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11892&stc=1

-> a,c,e and g are input ports (signed)

-> b, d, f and h are constants (signed)

-> multiple of this blocks are instantiated with different inputs and constants

One of the constant vectors derives to:

b=80

d=9

f=-70

h=-87

For stratixV synthesis this results in 2 DSP blocks as expected (0 Combs + 34 Regs + 2 DSPs). If I'm running the same design for arria10 synthesis there is only one DSP used plus additional logic (88 Combs + 34 Regs + 1 DSP). Logic seems to be used for constants 9 and 80. Using only DSPs without logic is mandatory for my design. How can I avoid this (optimization)?

StratixV synthesis with 15.1.1

Arria10 synthesis with 15.1.2 (Pro)

Help is greatly appreciated.

Altera_Forum · ‎02-26-2016

At first glance, I cant really understand why. It could just be a compiler bug with inference ie. you're not quite using the template expected. have you tried using separate intermediate signal outside of the clock process for the multiplication and addition, with only the final register in the process? Have you tried using intermediate variables instead?

I suggest raising a ticket with altera's mysupport.

Altera_Forum · ‎02-26-2016

--- Quote Start ---

At first glance, I cant really understand why. It could just be a compiler bug with inference ie. you're not quite using the template expected. have you tried using separate intermediate signal outside of the clock process for the multiplication and addition, with only the final register in the process? Have you tried using intermediate variables instead?

--- Quote End ---

I did. Same behavior with this piece of code:


  abcd <= (a * b) + (c * d);
  efgh <= (e * f) + (g * h);
  abcdefgh <= abcd + efgh;
  dataout <= abcdefgh_reg;
  p_register : process(clk)
  begin
    if rising_edge(clk) then
      abcdefgh_reg <= abcdefgh;
    end if;
  end process p_register;

Altera_Forum · ‎02-26-2016

I think this could be an issue for mysupport.