Data memory using LPM_RAM_DQ

[Altera_Forum]

Hi all! I have a problem in using LPM_RAM_DQ to make a datamemory for MIPS Pipeline R3000. I've tried the following VHDL code : 

 entity data_memory is     port ( clock : in std_logic;          ALUoutM : in std_logic_vector (31 downto 0);          writedataM : in std_logic_vector (31 downto 0);          mymemwriteM : in std_logic;          read_mem : out std_logic_vector (31 downto 0));  end data_memory;[/INDENT]   architecture behavior of data_memory is  COMPONENT lpm_ram_dq     GENERIC (LPM_WIDTH: POSITIVE;             LPM_TYPE: STRING := L_RAM_DQ;             LPM_WIDTHAD: POSITIVE;             LPM_NUMWORDS: natural := 0;             LPM_FILE: STRING := "UNUSED";             LPM_INDATA: STRING := "REGISTERED";             LPM_ADDRESS_CONTROL: STRING := "REGISTERED";             LPM_OUTDATA: STRING := "REGISTERED");  PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);  address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);             we: IN STD_LOGIC := '1';             inclock: IN STD_LOGIC := '1';             outclock: IN STD_LOGIC := '1';             q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));  END COMPONENT;[/INDENT]    signal tempdata : std_logic_vector (31 downto 0);  begin  label0: lpm_ram_dq  generic map (LPM_WIDTH                => 32,                  LPM_WIDTHAD            => 32,                  LPM_INDATA             => "REGISTERED",                  LPM_OUTDATA             => "UNREGISTERED",                  LPM_FILE                => "dmemory.mif"                  LPM_ADDRESS_CONTROL => "unregistered")    port map ( address => ALUoutM,                 we => mymemwriteM,                 inclock => clock,                 data => writedataM,                 q => tempdata);  read_mem <= tempdata;[/INDENT] end behavior; [/INDENT]  However when I tried to compile it using QuartusII v8, the process seemed stuck at 2% and my memory usage increased alarmingly to 1.4 GB in my task manager. Is there anything wrong with the above code? or is there any smarter way to realize a data memory. Thanks in advance :)

[Altera_Forum]

address width of 32 bits means 2^32 ram depth each location at 32 bits. 

i.e. trillion bits. Phenomenal size for fpga.

[Altera_Forum]

Ohh i see, so I won't be able to use lpm_ram_dq for realizing 32-bits address for a data memory? is there any alternative for it?

[Altera_Forum]

Use a smaller memory, with less address bits. You can still use a 32-bit address vector outside, and only map a small portion of the address space to the memory.