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Honored Contributor I
1,168 Views

Data skew constrain

In my design I need to sample the incoming serial data in 8 different registers simultaneously. The registers are clocked by different clocks (8 different phases of one clock). The design should select the correct clock phase for sampling. How can I constrain the data comming from PAD to arrive to the registers as simultaneously as it possible. Thanks

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Honored Contributor I
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The thing that I know is to set the Option of (fast input register) as ON in the assignment editor so that the deign uses io registers instead of general purpose registers.

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Honored Contributor I
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Thank You Kaz. 

I will try it. But I'm pesimistic it will help. There is one input comming to 8 registers. So one of registers will implemented as fast input register. What about others? Do You think it is possible to implement 8 fast input registers in one IO?
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Honored Contributor I
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You can't implement 8 fast input registers in one cell - the fast input register is in the IO cell itself - i.e. right at the pin. You could connect eight pins together externally and have your eight fast input registers that way. 

 

How fast is your clock(s)? Could you use one common clock at eight times the speed and use eight clock enables instead - i.e. each clock enable is active in turn for one clock cycle.
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Honored Contributor I
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Thanks batfink. 

The Data input is LVDS. To "spread" it to 8 different LVDS receivers is impossible (HW issue). 

The clock speed is 312MHz.
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Honored Contributor I
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Can you use an altlvds_rx SERDES?

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Honored Contributor I
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I got a funny idea but may be worth playing with it. 

declare 8 inout pins. drive all 8 pins continuously with your input data then 

read back from the 8 inouts setting all to fast registers...  

the signal will pass through always enabled tristate in all cases, hopefully with same delay. 

 

edit: 

Of course you can use serdes rx to recover data and clock but I assume the purpose is a DIY exercise to recover clock.
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Honored Contributor I
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312 MHz is a little on the quick side for my suggestion. 

 

I'll get my coat.
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Honored Contributor I
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Come into the input, then feed your 8 F/F and floorplan the 8 F/F to be right next to the I/O cell on the die. 

This should help control the route delays. 

 

The real challenge is that you will be using 8 different clocks (related by phase), each FF will need to be in a different LAB. 

 

To help control the route delays, you can then set a very "almost" undo-able SDC constraint on the incoming part to force the tool to work real hard to meet all the parallel timings. (turn on timing driven options). 

 

Good luck with this, and keep us informed.
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Honored Contributor I
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Hi All. 

To make long story short - it is working. 

The thing that made it working is Logic lock feature and Chip planer. 

Using Logic lock feature and Chip planer I constrained the problematic registers to be as close to Data in pad as possible. 

 

Thank You All
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