Hello All,
I am currently doing a design where i have generated a pll using megawizard in Quartus 12.1 SP1, the pll generates 5 clk out of which clkout 1 which is -165 degree phase shift is used to latch SdrDQ data from a Sdram Interface (125 MHz interface) and pll outclock 4 is -105 degree phase shift is used to generate Sdram Clock.
In first synthesis run when i generated using quartus the clock summary for sdrclk has .....FF_X88_Y1_N41 for SdrOe for arrival path summary assigned by tool.
to reduce some slack i reduced the phase of outclock 1 and compiled , the slack didnt changed much but the same sdroe component in arrival path summary has DDIOOECELL_X67_Y0_N56 .
My queries are
1) what is this DDIOOECELL ? although i tried to look for an answer couldnt get one.
2) how do FF changed to DDIOOECELL even though i have used the same QSF for second run?
3) how to remove this DDIOOECELL assignment from quartus , if anything to set in qsf file or like that?
Hope for reply so that i can conclude my design
