De0 sdram vhdl

[Altera_Forum]

Hi everybody,  

 I tried to write a VHDL code for the SDRAM controller based of the Hamster one in: http://hamsterworks.co.nz/mediawiki/index.php/simple_sdram_controller The next thing I would like to do is to write some code in VHDL that reads and writes to the SDRAM, I just need help to write the layer that make the interface with my controller. It would just have something like clock, address, ready, write/read, and data. I'm not yet familiar with this kind of interfaces. I am having problems understanding how this works. If anyone has more experience with this, I would appreciate your help. Thanks in advance,  Best regards,

[Altera_Forum]

Start reading datasheet of memory chip on the DE0 Nano board right now, start coding and by the end of the week you'll have nice working controller. Or just use search: http://www.alteraforum.com/forum/showthread.php?t=45927&p=189720#post189720

[Altera_Forum]

Thank you Linas for your reply. I understood the data-sheet of my chip and also write the code. The problem that I have is how to generate pattern to test my memory. 

I used a timer to generate an interruption, when it's activated I write a DATA in a specified address. And when the interruption is deactivated I read the data that was written. Unfortunately, it doesn't work for me. Note: i did not use nios neither jtag, only VHDL coding. Best regards

[Altera_Forum]

You can initialize on-chip memory with known good values, write them to SDRAM, read and check against your known good values. You can use PRBS generator module form UDP Offload example.